HK69493A - Process for fabricating a semiconductor integrated circuit device having misfets - Google Patents

Process for fabricating a semiconductor integrated circuit device having misfets Download PDF

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Publication number
HK69493A
HK69493A HK694/93A HK69493A HK69493A HK 69493 A HK69493 A HK 69493A HK 694/93 A HK694/93 A HK 694/93A HK 69493 A HK69493 A HK 69493A HK 69493 A HK69493 A HK 69493A
Authority
HK
Hong Kong
Prior art keywords
gate electrode
conductivity type
channel
source
drain regions
Prior art date
Application number
HK694/93A
Other languages
German (de)
English (en)
Inventor
Shuji Ikeda
Atsuyoshi Koike
Satoshi Meguro
Kousuke Okuyama
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of HK69493A publication Critical patent/HK69493A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8312—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Claims (5)

  1. Procédé de fabrication d'un dispositif de circuit intégré à semiconducteurs possédant des MISFET (1, 2) de premier et second types de conductivité , comportant les étapes consistant à    former une seconde région semiconductrice (15) du second type de conductivité dans une première région semiconductrice (11) du premier type de conductivité formée dans un substrat semiconducteur (3),    former des électrodes de grille (5, 12), l'électrode de grille (12) du MISFET (2) du second type de conductivité étant formée au-dessus de ladite seconde région semiconductrice (15), et    former des régions de source et de drain (7, 13) en introduisant des impuretés dans ladite première région semiconductrice (11), les régions de source et de drain (13) dudit MISFET (2) du second type de conductivité faisant corps avec ladite seconde région semiconductrice (15), et espacées de et de part et d'autre de ladite électrode de grille (12) dudit MISFET (2) du second type de conductivité, caractérisé en ce que des entretoises de paroi latérale (6, 16) sont formées sur les deux parois latérales desdites électrodes de grille (5, 12) en déposant une pellicule isolante et en gravant de façon anisotropique la pellicule par gravure ionique réactive, et en ce que l'impureté pour former les régions de source et de drain (13) du MISFET (2) du second type de conductivité est introduite en utilisant ladite électrode de grille (12) et les entretoises de paroi latérale (16) comme masque.
  2. Procédé selon la revendication 1, dans lequel ladite région semiconductrice (15) est formée en introduisant une impureté pour régler la tension de seuil dudit MISFET (1) du premier type de conductivité.
  3. Procédé selon la revendication 1 ou 2, dans lequel ledit MISFET (1) du premier type de conductivité est formé dans une région semiconductrice (4) du second type de conductivité formée dans ledit substrat semiconducteur (3).
  4. Procédé selon l'une quelconque des revendications 1 à 3, dans lequel lesdits MISFET (1, 2) des premier et second types de conductivité sont des MOSFET à canal N et P, respectivement.
  5. Procédé selon la revendication 4, dans lequel les régions de source et de drain (7) dudit MOSFET à canal N (1) possèdent une structure LDD réalisée en    formant une région de concentration en impuretés faible (9) en introduisant une impureté en utilisant ladite électrode de grille (5) comme masque, et    en formant une région de concentration en impuretés élevée (8) en introduisant une impureté en utilisant ladite électrode de grille (5) et lesdites entretoises de paroi latérale (6) comme masque.
HK694/93A 1984-12-03 1993-07-15 Process for fabricating a semiconductor integrated circuit device having misfets HK69493A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59254010A JPS61133656A (ja) 1984-12-03 1984-12-03 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
HK69493A true HK69493A (en) 1993-07-23

Family

ID=17259003

Family Applications (1)

Application Number Title Priority Date Filing Date
HK694/93A HK69493A (en) 1984-12-03 1993-07-15 Process for fabricating a semiconductor integrated circuit device having misfets

Country Status (7)

Country Link
EP (1) EP0187260B1 (fr)
JP (1) JPS61133656A (fr)
KR (1) KR940000521B1 (fr)
CN (1) CN1004777B (fr)
DE (1) DE3583668D1 (fr)
HK (1) HK69493A (fr)
SG (1) SG43193G (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263137A (ja) * 1985-05-07 1986-11-21 Hitachi Ltd 半導体装置
ATE78364T1 (de) * 1985-12-04 1992-08-15 Advanced Micro Devices Inc Feldeffekttransistor.
JPS6473676A (en) * 1987-09-16 1989-03-17 Hitachi Ltd Semiconductor integrated circuit device
IT1223571B (it) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte
NL8802219A (nl) * 1988-09-09 1990-04-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
JP2849923B2 (ja) * 1989-06-05 1999-01-27 猛英 白土 半導体装置
JPH03232231A (ja) * 1990-02-08 1991-10-16 Toshiba Corp 半導体装置
US6656797B2 (en) * 2001-12-31 2003-12-02 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation
CN101312187B (zh) * 2007-05-21 2011-07-13 中芯国际集成电路制造(上海)有限公司 半导体器件逻辑电路
CN101312193B (zh) * 2007-05-21 2011-07-13 中芯国际集成电路制造(上海)有限公司 半导体器件逻辑电路
JP5623898B2 (ja) * 2010-12-21 2014-11-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN104701356B (zh) 2013-12-06 2018-01-12 无锡华润上华科技有限公司 半导体器件及其制备方法
TWI731700B (zh) * 2020-05-27 2021-06-21 新唐科技股份有限公司 具有埋層結構的高壓半導體裝置
CN114649414A (zh) * 2020-12-18 2022-06-21 苏州华太电子技术有限公司 高密度DreaMOS器件及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
JPS5736856A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Manufacture of complementary type insulated gate field effect semiconductor device
JPS57107067A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Manufacture of semiconductor device
JPS5972759A (ja) * 1982-10-20 1984-04-24 Toshiba Corp 半導体装置の製造方法
EP0113540A3 (fr) * 1982-12-10 1985-06-05 Western Electric Company, Incorporated Dispositifs semi-conducteurs et procédé pour leur fabrication
JPS6046804B2 (ja) * 1983-04-22 1985-10-18 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
CN85108671A (zh) 1986-06-10
DE3583668D1 (de) 1991-09-05
KR860005450A (ko) 1986-07-23
EP0187260B1 (fr) 1991-07-31
JPS61133656A (ja) 1986-06-20
EP0187260A2 (fr) 1986-07-16
EP0187260A3 (en) 1987-01-07
SG43193G (en) 1993-06-25
CN1004777B (zh) 1989-07-12
KR940000521B1 (ko) 1994-01-21

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Legal Events

Date Code Title Description
NR Patent deemed never to have been added to the register under section 13(7) of patents (transitional arrangements) rules