IL109921A - Method and apparatus for configuring memory circuits - Google Patents

Method and apparatus for configuring memory circuits

Info

Publication number
IL109921A
IL109921A IL109921A IL10992194A IL109921A IL 109921 A IL109921 A IL 109921A IL 109921 A IL109921 A IL 109921A IL 10992194 A IL10992194 A IL 10992194A IL 109921 A IL109921 A IL 109921A
Authority
IL
Israel
Prior art keywords
access
memory
port
memory circuits
read
Prior art date
Application number
IL109921A
Other languages
English (en)
Other versions
IL109921A0 (en
Original Assignee
Quickturn Design Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems filed Critical Quickturn Design Systems
Publication of IL109921A0 publication Critical patent/IL109921A0/xx
Publication of IL109921A publication Critical patent/IL109921A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IL109921A 1993-06-24 1994-06-07 Method and apparatus for configuring memory circuits IL109921A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8205193A 1993-06-24 1993-06-24

Publications (2)

Publication Number Publication Date
IL109921A0 IL109921A0 (en) 1994-10-07
IL109921A true IL109921A (en) 1997-09-30

Family

ID=22168735

Family Applications (1)

Application Number Title Priority Date Filing Date
IL109921A IL109921A (en) 1993-06-24 1994-06-07 Method and apparatus for configuring memory circuits

Country Status (9)

Country Link
US (1) US5940603A (it)
JP (1) JPH0773066A (it)
CA (1) CA2126621A1 (it)
DE (1) DE4420610A1 (it)
FR (1) FR2709006A1 (it)
GB (1) GB2280524A (it)
IL (1) IL109921A (it)
IT (1) IT1273001B (it)
SE (1) SE9402213A0 (it)

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US6754130B1 (en) 2002-12-23 2004-06-22 Hewlett-Packard Development Company, Lp. Memory having multiple write ports and write insert unit, and method of operation
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US6813215B2 (en) * 2002-12-23 2004-11-02 Hewlett-Packard Development Company, L.P. Memory having multiple write ports and method of operation
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US7440884B2 (en) * 2003-01-23 2008-10-21 Quickturn Design Systems, Inc. Memory rewind and reconstruction for hardware emulator
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US7425841B2 (en) 2004-02-14 2008-09-16 Tabula Inc. Configurable circuits, IC's, and systems
US7167025B1 (en) 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
US7640155B2 (en) * 2004-06-01 2009-12-29 Quickturn Design Systems, Inc. Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications
US7721036B2 (en) * 2004-06-01 2010-05-18 Quickturn Design Systems Inc. System and method for providing flexible signal routing and timing
US7282950B1 (en) * 2004-11-08 2007-10-16 Tabula, Inc. Configurable IC's with logic resources with offset connections
US7743085B2 (en) 2004-11-08 2010-06-22 Tabula, Inc. Configurable IC with large carry chains
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7317331B2 (en) 2004-11-08 2008-01-08 Tabula, Inc. Reconfigurable IC that has sections running at different reconfiguration rates
US7315993B2 (en) * 2004-11-30 2008-01-01 Lsi Logic Corporation Verification of RRAM tiling netlist
US7530033B2 (en) 2005-03-15 2009-05-05 Tabula, Inc. Method and apparatus for decomposing functions in a configurable IC
US7298169B2 (en) * 2005-03-15 2007-11-20 Tabula, Inc Hybrid logic/interconnect circuit in a configurable IC
US7825684B2 (en) 2005-03-15 2010-11-02 Tabula, Inc. Variable width management for a memory of a configurable IC
US7230869B1 (en) 2005-03-15 2007-06-12 Jason Redgrave Method and apparatus for accessing contents of memory cells
US7243314B2 (en) * 2005-04-14 2007-07-10 Inventec Corporation Window operation interface for graphically revising electrical constraint set and method of using the same
US7599242B2 (en) 2005-09-28 2009-10-06 Hynix Semiconductor Inc. Test circuit for multi-port memory device
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US8090568B2 (en) * 2006-02-21 2012-01-03 Cadence Design Systems, Inc. Hardware emulator having a variable input primitive
US7797497B1 (en) 2006-03-08 2010-09-14 Tabula, Inc. System and method for providing more logical memory ports than physical memory ports
US7694083B1 (en) * 2006-03-08 2010-04-06 Tabula, Inc. System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
US7587697B1 (en) * 2006-12-12 2009-09-08 Tabula, Inc. System and method of mapping memory blocks in a configurable integrated circuit
US7930666B1 (en) 2006-12-12 2011-04-19 Tabula, Inc. System and method of providing a memory hierarchy
US7525344B2 (en) 2007-03-20 2009-04-28 Tabula, Inc. Configurable IC having a routing fabric with storage elements
US7535252B1 (en) 2007-03-22 2009-05-19 Tabula, Inc. Configurable ICs that conditionally transition through configuration data sets
EP2201569A4 (en) * 2007-09-06 2011-07-13 Tabula Inc CONFIGURATION CONTEXT CHANGER
WO2010033263A1 (en) 2008-09-17 2010-03-25 Tabula, Inc. Controllable storage elements for an ic
US8443335B2 (en) * 2009-12-09 2013-05-14 Agnisys, Inc. Apparatus and method for circuit design
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
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Also Published As

Publication number Publication date
SE9402213D0 (sv) 1994-06-22
ITRM940407A0 (it) 1994-06-22
IL109921A0 (en) 1994-10-07
IT1273001B (it) 1997-07-01
FR2709006A1 (fr) 1995-02-17
US5940603A (en) 1999-08-17
GB9411924D0 (en) 1994-08-03
SE9402213A0 (en) 1995-02-24
GB2280524A (en) 1995-02-01
CA2126621A1 (en) 1994-12-25
JPH0773066A (ja) 1995-03-17
DE4420610A1 (de) 1995-01-26
SE9402213L (it)
ITRM940407A1 (it) 1995-12-22

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