ITRM940407A0 - "procedimento ed apparecchio per la raffigurazione di circuiti di memoria". - Google Patents

"procedimento ed apparecchio per la raffigurazione di circuiti di memoria".

Info

Publication number
ITRM940407A0
ITRM940407A0 ITRM940407A ITRM940407A ITRM940407A0 IT RM940407 A0 ITRM940407 A0 IT RM940407A0 IT RM940407 A ITRM940407 A IT RM940407A IT RM940407 A ITRM940407 A IT RM940407A IT RM940407 A0 ITRM940407 A0 IT RM940407A0
Authority
IT
Italy
Prior art keywords
representation
procedure
memory circuits
circuits
memory
Prior art date
Application number
ITRM940407A
Other languages
English (en)
Inventor
Thomas B Huang
Original Assignee
Pie Design System Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pie Design System Inc filed Critical Pie Design System Inc
Publication of ITRM940407A0 publication Critical patent/ITRM940407A0/it
Publication of ITRM940407A1 publication Critical patent/ITRM940407A1/it
Application granted granted Critical
Publication of IT1273001B publication Critical patent/IT1273001B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
ITRM940407A 1993-06-24 1994-06-22 "procedimento ed apparecchio per la configurazione di circuiti di memoria". IT1273001B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8205193A 1993-06-24 1993-06-24

Publications (3)

Publication Number Publication Date
ITRM940407A0 true ITRM940407A0 (it) 1994-06-22
ITRM940407A1 ITRM940407A1 (it) 1995-12-22
IT1273001B IT1273001B (it) 1997-07-01

Family

ID=22168735

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM940407A IT1273001B (it) 1993-06-24 1994-06-22 "procedimento ed apparecchio per la configurazione di circuiti di memoria".

Country Status (9)

Country Link
US (1) US5940603A (it)
JP (1) JPH0773066A (it)
CA (1) CA2126621A1 (it)
DE (1) DE4420610A1 (it)
FR (1) FR2709006A1 (it)
GB (1) GB2280524A (it)
IL (1) IL109921A (it)
IT (1) IT1273001B (it)
SE (1) SE9402213A0 (it)

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US7035787B2 (en) * 2001-10-30 2006-04-25 Mentor Graphics Corporation Emulation components and system including distributed routing and configuration of emulation resources
US7130788B2 (en) * 2001-10-30 2006-10-31 Mentor Graphics Corporation Emulation components and system including distributed event monitoring, and testing of an IC design under emulation
US7062427B2 (en) * 2001-12-27 2006-06-13 John Stephen Walther Batch editor for netlists described in a hardware description language
US6754130B1 (en) 2002-12-23 2004-06-22 Hewlett-Packard Development Company, Lp. Memory having multiple write ports and write insert unit, and method of operation
US6654308B1 (en) 2002-12-23 2003-11-25 Hewlett-Packard Development Company, Lp. Memory having multiple write ports and multiple control memory units, and method of operation
US6813215B2 (en) * 2002-12-23 2004-11-02 Hewlett-Packard Development Company, L.P. Memory having multiple write ports and method of operation
JP4238124B2 (ja) 2003-01-07 2009-03-11 積水化学工業株式会社 硬化性樹脂組成物、接着性エポキシ樹脂ペースト、接着性エポキシ樹脂シート、導電接続ペースト、導電接続シート及び電子部品接合体
US7440884B2 (en) * 2003-01-23 2008-10-21 Quickturn Design Systems, Inc. Memory rewind and reconstruction for hardware emulator
GB2403574B (en) * 2003-07-03 2005-05-11 Micron Technology Inc Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
US7425841B2 (en) 2004-02-14 2008-09-16 Tabula Inc. Configurable circuits, IC's, and systems
US7167025B1 (en) 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
US7640155B2 (en) * 2004-06-01 2009-12-29 Quickturn Design Systems, Inc. Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications
US7721036B2 (en) * 2004-06-01 2010-05-18 Quickturn Design Systems Inc. System and method for providing flexible signal routing and timing
US7282950B1 (en) * 2004-11-08 2007-10-16 Tabula, Inc. Configurable IC's with logic resources with offset connections
US7743085B2 (en) 2004-11-08 2010-06-22 Tabula, Inc. Configurable IC with large carry chains
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7317331B2 (en) 2004-11-08 2008-01-08 Tabula, Inc. Reconfigurable IC that has sections running at different reconfiguration rates
US7315993B2 (en) * 2004-11-30 2008-01-01 Lsi Logic Corporation Verification of RRAM tiling netlist
US7530033B2 (en) 2005-03-15 2009-05-05 Tabula, Inc. Method and apparatus for decomposing functions in a configurable IC
US7298169B2 (en) * 2005-03-15 2007-11-20 Tabula, Inc Hybrid logic/interconnect circuit in a configurable IC
US7825684B2 (en) 2005-03-15 2010-11-02 Tabula, Inc. Variable width management for a memory of a configurable IC
US7230869B1 (en) 2005-03-15 2007-06-12 Jason Redgrave Method and apparatus for accessing contents of memory cells
US7243314B2 (en) * 2005-04-14 2007-07-10 Inventec Corporation Window operation interface for graphically revising electrical constraint set and method of using the same
US7599242B2 (en) 2005-09-28 2009-10-06 Hynix Semiconductor Inc. Test circuit for multi-port memory device
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US8090568B2 (en) * 2006-02-21 2012-01-03 Cadence Design Systems, Inc. Hardware emulator having a variable input primitive
US7797497B1 (en) 2006-03-08 2010-09-14 Tabula, Inc. System and method for providing more logical memory ports than physical memory ports
US7694083B1 (en) * 2006-03-08 2010-04-06 Tabula, Inc. System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
US7587697B1 (en) * 2006-12-12 2009-09-08 Tabula, Inc. System and method of mapping memory blocks in a configurable integrated circuit
US7930666B1 (en) 2006-12-12 2011-04-19 Tabula, Inc. System and method of providing a memory hierarchy
US7525344B2 (en) 2007-03-20 2009-04-28 Tabula, Inc. Configurable IC having a routing fabric with storage elements
US7535252B1 (en) 2007-03-22 2009-05-19 Tabula, Inc. Configurable ICs that conditionally transition through configuration data sets
EP2201569A4 (en) * 2007-09-06 2011-07-13 Tabula Inc CONFIGURATION CONTEXT CHANGER
WO2010033263A1 (en) 2008-09-17 2010-03-25 Tabula, Inc. Controllable storage elements for an ic
US8443335B2 (en) * 2009-12-09 2013-05-14 Agnisys, Inc. Apparatus and method for circuit design
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
WO2013071183A1 (en) 2011-11-11 2013-05-16 Tabula, Inc. Content addressable memory in integrated circuit

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Also Published As

Publication number Publication date
SE9402213D0 (sv) 1994-06-22
IL109921A (en) 1997-09-30
IL109921A0 (en) 1994-10-07
IT1273001B (it) 1997-07-01
FR2709006A1 (fr) 1995-02-17
US5940603A (en) 1999-08-17
GB9411924D0 (en) 1994-08-03
SE9402213A0 (en) 1995-02-24
GB2280524A (en) 1995-02-01
CA2126621A1 (en) 1994-12-25
JPH0773066A (ja) 1995-03-17
DE4420610A1 (de) 1995-01-26
SE9402213L (it)
ITRM940407A1 (it) 1995-12-22

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