IT1214615B - Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione. - Google Patents

Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione.

Info

Publication number
IT1214615B
IT1214615B IT8521201A IT2120185A IT1214615B IT 1214615 B IT1214615 B IT 1214615B IT 8521201 A IT8521201 A IT 8521201A IT 2120185 A IT2120185 A IT 2120185A IT 1214615 B IT1214615 B IT 1214615B
Authority
IT
Italy
Prior art keywords
punch
limitation
mos transistor
channel mos
training process
Prior art date
Application number
IT8521201A
Other languages
English (en)
Other versions
IT8521201A0 (it
Inventor
Paolo Cappelleti
Marina Tosi
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8521201A priority Critical patent/IT1214615B/it
Publication of IT8521201A0 publication Critical patent/IT8521201A0/it
Priority to DE8686200921T priority patent/DE3666645D1/de
Priority to EP86200921A priority patent/EP0209166B1/en
Priority to JP61140430A priority patent/JPS6249667A/ja
Application granted granted Critical
Publication of IT1214615B publication Critical patent/IT1214615B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
IT8521201A 1985-06-19 1985-06-19 Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione. IT1214615B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8521201A IT1214615B (it) 1985-06-19 1985-06-19 Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione.
DE8686200921T DE3666645D1 (en) 1985-06-19 1986-05-27 N channel mos transistor with limitation of punch-through effect and formation process thereof
EP86200921A EP0209166B1 (en) 1985-06-19 1986-05-27 N channel mos transistor with limitation of punch-through effect and formation process thereof
JP61140430A JPS6249667A (ja) 1985-06-19 1986-06-18 Ｎチヤンネルｍｏｓトランジスタおよびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8521201A IT1214615B (it) 1985-06-19 1985-06-19 Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione.

Publications (2)

Publication Number Publication Date
IT8521201A0 IT8521201A0 (it) 1985-06-19
IT1214615B true IT1214615B (it) 1990-01-18

Family

ID=11178292

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8521201A IT1214615B (it) 1985-06-19 1985-06-19 Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione.

Country Status (4)

Country Link
EP (1) EP0209166B1 (it)
JP (1) JPS6249667A (it)
DE (1) DE3666645D1 (it)
IT (1) IT1214615B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254537A (ja) * 1988-08-18 1990-02-23 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
KR0139773B1 (ko) * 1992-08-11 1998-06-01 사또오 후미오 반도체 집적 회로 장치 및 그 제조 방법
US5371394A (en) * 1993-11-15 1994-12-06 Motorola, Inc. Double implanted laterally diffused MOS device and method thereof
WO2010086153A1 (en) * 2009-01-30 2010-08-05 Advanced Micro Devices, Inc Graded well implantation for asymmetric transistors having reduced gate electrode pitches
DE102009006885B4 (de) * 2009-01-30 2011-09-22 Advanced Micro Devices, Inc. Verfahren zum Erzeugen einer abgestuften Wannenimplantation für asymmetrische Transistoren mit kleinen Gateelektrodenabständen und Halbleiterbauelemente

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3279662D1 (en) * 1981-12-30 1989-06-01 Thomson Components Mostek Corp Triple diffused short channel device structure
JPS58153370A (ja) * 1982-03-08 1983-09-12 Nec Corp Ｍｏｓトランジスタ及びその製造方法
DE3208500A1 (de) * 1982-03-09 1983-09-15 Siemens AG, 1000 Berlin und 8000 München Spannungsfester mos-transistor fuer hoechstintegrierte schaltungen
JPS5972174A (ja) * 1982-10-18 1984-04-24 Toshiba Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP0209166B1 (en) 1989-10-25
DE3666645D1 (en) 1989-11-30
EP0209166A1 (en) 1987-01-21
JPS6249667A (ja) 1987-03-04
IT8521201A0 (it) 1985-06-19

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