IT1214808B - Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli - Google Patents

Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli

Info

Publication number
IT1214808B
IT1214808B IT8406633A IT663384A IT1214808B IT 1214808 B IT1214808 B IT 1214808B IT 8406633 A IT8406633 A IT 8406633A IT 663384 A IT663384 A IT 663384A IT 1214808 B IT1214808 B IT 1214808B
Authority
IT
Italy
Prior art keywords
monoli
tico
formation
buried layer
collector region
Prior art date
Application number
IT8406633A
Other languages
English (en)
Other versions
IT8406633A0 (it
Inventor
Musumeci Salvatore
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8406633A priority Critical patent/IT1214808B/it
Publication of IT8406633A0 publication Critical patent/IT8406633A0/it
Priority to FR8518395A priority patent/FR2575330B1/fr
Priority to GB08530729A priority patent/GB2169444B/en
Priority to DE3545040A priority patent/DE3545040C2/de
Priority to US06/811,754 priority patent/US4721684A/en
Priority to JP60285844A priority patent/JPS61181161A/ja
Application granted granted Critical
Publication of IT1214808B publication Critical patent/IT1214808B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/15—Diffusion of dopants within, into or out of semiconductor bodies or layers from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
IT8406633A 1984-12-20 1984-12-20 Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli IT1214808B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT8406633A IT1214808B (it) 1984-12-20 1984-12-20 Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli
FR8518395A FR2575330B1 (fr) 1984-12-20 1985-12-12 Procede pour la formation d'une couche enterree et d'une region de collecteur dans un dispositif monolithique a semi-conducteur
GB08530729A GB2169444B (en) 1984-12-20 1985-12-13 Improvements in or relating to methods of making semiconductor devices
DE3545040A DE3545040C2 (de) 1984-12-20 1985-12-19 Verfahren zur Herstellung einer vergrabenen Schicht und einer Kollektorzone in einer monolithischen Halbleitervorrichtung
US06/811,754 US4721684A (en) 1984-12-20 1985-12-20 Method for forming a buried layer and a collector region in a monolithic semiconductor device
JP60285844A JPS61181161A (ja) 1984-12-20 1985-12-20 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8406633A IT1214808B (it) 1984-12-20 1984-12-20 Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli

Publications (2)

Publication Number Publication Date
IT8406633A0 IT8406633A0 (it) 1984-12-20
IT1214808B true IT1214808B (it) 1990-01-18

Family

ID=11121628

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8406633A IT1214808B (it) 1984-12-20 1984-12-20 Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli

Country Status (6)

Country Link
US (1) US4721684A (it)
JP (1) JPS61181161A (it)
DE (1) DE3545040C2 (it)
FR (1) FR2575330B1 (it)
GB (1) GB2169444B (it)
IT (1) IT1214808B (it)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4936928A (en) * 1985-11-27 1990-06-26 Raytheon Company Semiconductor device
IT1215024B (it) * 1986-10-01 1990-01-31 Sgs Microelettronica Spa Processo per la formazione di un dispositivo monolitico a semiconduttore di alta tensione
US4855244A (en) * 1987-07-02 1989-08-08 Texas Instruments Incorporated Method of making vertical PNP transistor in merged bipolar/CMOS technology
IT1221587B (it) * 1987-09-07 1990-07-12 S G S Microelettronics Spa Procedimento di fabbricazione di un dispositivo integrato monolitico a semiconduttore avente strati epitas siali a bassa concentrazione di impurita'
IT1217323B (it) * 1987-12-22 1990-03-22 Sgs Microelettronica Spa Struttura integrata di transistor bipolare di potenza di alta tensione e di transistor mos di potenza di bassa tensione nella configurazione"emitter switching"e relativo processo di fabbricazione
IT1217322B (it) * 1987-12-22 1990-03-22 Sgs Microelettronica Spa Procedimento di fabbricazione di un dispositivo nonolitico a semiconduttope comprendente almeno un transistor di un circuito integrato di comando e un transistor di rotenza in tegrato nella stessa piastrina
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
USRE38510E1 (en) * 1987-12-22 2004-05-04 Stmicroelectronics Srl Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip
US5246871A (en) * 1989-06-16 1993-09-21 Sgs-Thomson Microelectronics S.R.L. Method of manufacturing a semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip
US5024967A (en) * 1989-06-30 1991-06-18 At&T Bell Laboratories Doping procedures for semiconductor devices
US5262345A (en) * 1990-01-25 1993-11-16 Analog Devices, Inc. Complimentary bipolar/CMOS fabrication method
EP0439899A3 (en) * 1990-01-25 1991-11-06 Precision Monolithics Inc. Complementary bipolar transistors compatible with cmos process
IT1241050B (it) * 1990-04-20 1993-12-29 Cons Ric Microelettronica Processo di formazione di una regione sepolta di drain o di collettore in dispositivi monolitici a semiconduttore.
US5442191A (en) * 1990-09-05 1995-08-15 Yale University Isotopically enriched semiconductor devices
US5144409A (en) * 1990-09-05 1992-09-01 Yale University Isotopically enriched semiconductor devices
DE69125390T2 (de) * 1991-07-03 1997-08-28 Cons Ric Microelettronica Laterale Bipolartransistorstruktur mit integriertem Kontrollschaltkreis und integriertem Leistungstransistor und deren Herstellungsprozess
US5633180A (en) * 1995-06-01 1997-05-27 Harris Corporation Method of forming P-type islands over P-type buried layer
US6566217B1 (en) * 1996-01-16 2003-05-20 Mitsubishi Denki Kabushiki Kaisha Manufacturing process for semiconductor device
EP0809294B1 (en) * 1996-05-21 2002-01-02 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Power semiconductor device structure with vertical PNP transistor
SE519975C2 (sv) 1999-06-23 2003-05-06 Ericsson Telefon Ab L M Halvledarstruktur för högspänningshalvledarkomponenter
DE10044838C2 (de) * 2000-09-11 2002-08-08 Infineon Technologies Ag Halbleiterbauelement und Verfahren zur Herstellung eines solchen
US6894366B2 (en) 2000-10-10 2005-05-17 Texas Instruments Incorporated Bipolar junction transistor with a counterdoped collector region
JP4775683B2 (ja) * 2003-09-29 2011-09-21 オンセミコンダクター・トレーディング・リミテッド 半導体集積回路装置
KR102419162B1 (ko) 2015-03-17 2022-07-11 삼성전자주식회사 패턴 검사 방법 및 그를 사용하는 기판 제조 장치

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3249831A (en) * 1963-01-04 1966-05-03 Westinghouse Electric Corp Semiconductor controlled rectifiers with a p-n junction having a shallow impurity concentration gradient
US3576475A (en) * 1968-08-29 1971-04-27 Texas Instruments Inc Field effect transistors for integrated circuits and methods of manufacture
BE758683A (fr) * 1969-11-10 1971-05-10 Ibm Procede de fabrication d'un dispositif monolithique auto-isolant et structure de transistor a socle
US3812519A (en) * 1970-02-07 1974-05-21 Tokyo Shibaura Electric Co Silicon double doped with p and as or b and as
IT947674B (it) * 1971-04-28 1973-05-30 Ibm Tecnica di diffusione epitassiale per la fabbricazione di transisto ri bipolari e transistori fet
US3971059A (en) * 1974-09-23 1976-07-20 National Semiconductor Corporation Complementary bipolar transistors having collector diffused isolation
US4132573A (en) * 1977-02-08 1979-01-02 Murata Manufacturing Co., Ltd. Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion
DE2710878A1 (de) * 1977-03-12 1978-09-14 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer an der oberflaeche eines halbleiterkoerpers aus silicium liegenden zone einer monolithisch integrierten i hoch 2 l-schaltung
JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture
ZA785953B (en) * 1977-11-03 1979-09-26 Int Computers Ltd Integrated circuits and methods of manufacture thereof
JPS54128268A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Multi-diffusion method of impurity
GB2023340B (en) * 1978-06-01 1982-09-02 Mitsubishi Electric Corp Integrated circuits
JPS5734357A (en) * 1980-08-09 1982-02-24 Sanken Electric Co Ltd Semiconductor integrated circuit
JPS57106047A (en) * 1980-12-23 1982-07-01 Sony Corp Manufacture of semiconductor integrated circuit device
NL8104862A (nl) * 1981-10-28 1983-05-16 Philips Nv Halfgeleiderinrichting, en werkwijze ter vervaardiging daarvan.

Also Published As

Publication number Publication date
IT8406633A0 (it) 1984-12-20
FR2575330B1 (fr) 1989-08-18
GB8530729D0 (en) 1986-01-22
FR2575330A1 (fr) 1986-06-27
JPS61181161A (ja) 1986-08-13
DE3545040A1 (de) 1986-06-26
DE3545040C2 (de) 1995-07-20
GB2169444A (en) 1986-07-09
US4721684A (en) 1988-01-26
GB2169444B (en) 1988-11-30

Similar Documents

Publication Publication Date Title
IT1214808B (it) Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli
DE69308727D1 (de) Herstellungsverfahren von einer Halbleitervorrichtung mit einer begrabenen Kontaktstruktur
DE3574080D1 (en) Silicon semiconductor substrate with an insulating layer embedded therein and method for forming the same
EP0315803A3 (en) A dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof
EP0213910A3 (en) Semiconductor device free from the current leakage through a semiconductor layer and method for manufacturing same
KR860001495A (ko) 반도체장치 및 그 제조방법
EP0187662A3 (en) Monolithically integrated semiconductor optical device and method of fabricating same
DE69323628D1 (de) Chip-verbindung mit gasdurchlässiger ätzsperrschicht
BR8500644A (pt) Processo para eletrogalvanizar um material sobre a primeira superficie de um dispositivo semicondutor
KR860002135A (ko) 반도체기판의 주표면에 凹형 도랑이 형성된 반도체장치 및 그 제조방법
EP0273715A3 (en) Method for forming metal layer and semiconductor device formed thereby
KR850006258A (ko) 반도체장치 제조방법
KR860006844A (ko) 반도체장치 및 그 제조방법
EP0165427A3 (en) Semiconductor package substrate and manufacturing process
AU583423B2 (en) Semiconductor device free from the electrical shortage through a semiconductor layer and method for manufacturing same
KR860005438A (ko) 반도체칩과 기판과의 접합구조가 개선된 반도체장치
EP0534746A3 (en) Method of fabricating a trench structure in a semiconductor substrate
HUT47742A (en) Method and device for detecting thickness of layer of the semiconductor layer structures
GB2182262B (en) High-oxygen-content silicon monocrystal substrate for semiconductor devices and production method therefor
KR860000710A (ko) 반도체장치 제조방법
KR860005437A (ko) 반도체장치의 제조방법
DE3572423D1 (en) Semiconductor device having a polycrystalline silicon interconnection layer and method for its manufacture
ES544481A0 (es) Un dispositivo fotovoltaico semiconductor amorfo y mejorado
EP0216017A3 (en) Method of manufacturing a semiconductor device including forming a multi-level interconnection layer
EP0208209A3 (en) A buried heterostructure semiconductor laser and a process of the fabrication of the same

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227