IT1217104B - Circuito integrato cmos a due alimentazioni con un transistore mos integrato di protezione contro il <<latch-up>>. - Google Patents

Circuito integrato cmos a due alimentazioni con un transistore mos integrato di protezione contro il <<latch-up>>.

Info

Publication number
IT1217104B
IT1217104B IT8783609A IT8360987A IT1217104B IT 1217104 B IT1217104 B IT 1217104B IT 8783609 A IT8783609 A IT 8783609A IT 8360987 A IT8360987 A IT 8360987A IT 1217104 B IT1217104 B IT 1217104B
Authority
IT
Italy
Prior art keywords
latch
mos transistor
protection against
integrated circuit
power cmos
Prior art date
Application number
IT8783609A
Other languages
English (en)
Other versions
IT8783609A0 (it
Inventor
Carlo Dallavalle
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT8783609A priority Critical patent/IT1217104B/it
Publication of IT8783609A0 publication Critical patent/IT8783609A0/it
Priority to GB8804099A priority patent/GB2202403B/en
Priority to US07/159,267 priority patent/US4871927A/en
Priority to JP63047343A priority patent/JPS63228663A/ja
Priority to DE3806951A priority patent/DE3806951C2/de
Application granted granted Critical
Publication of IT1217104B publication Critical patent/IT1217104B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT8783609A 1987-03-03 1987-03-03 Circuito integrato cmos a due alimentazioni con un transistore mos integrato di protezione contro il <<latch-up>>. IT1217104B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8783609A IT1217104B (it) 1987-03-03 1987-03-03 Circuito integrato cmos a due alimentazioni con un transistore mos integrato di protezione contro il <<latch-up>>.
GB8804099A GB2202403B (en) 1987-03-03 1988-02-23 Latch-up prevention in a two supplies, cmos integrated circuit by means of a single integrated mos transistor
US07/159,267 US4871927A (en) 1987-03-03 1988-02-23 Latch-up prevention in a two-power-supply CMOS integrated circuit by means of a single integrated MOS transistor
JP63047343A JPS63228663A (ja) 1987-03-03 1988-02-29 単一の集積されたｍｏｓトランジスタによる２個のサプライを有するｃｍｏｓ集積回路のラッチアップの防止方法
DE3806951A DE3806951C2 (de) 1987-03-03 1988-03-03 Integrierte Schaltung mit CMOS-Strukturen für zwei Versorgungsspannungen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8783609A IT1217104B (it) 1987-03-03 1987-03-03 Circuito integrato cmos a due alimentazioni con un transistore mos integrato di protezione contro il <<latch-up>>.

Publications (2)

Publication Number Publication Date
IT8783609A0 IT8783609A0 (it) 1987-03-03
IT1217104B true IT1217104B (it) 1990-03-14

Family

ID=11323082

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8783609A IT1217104B (it) 1987-03-03 1987-03-03 Circuito integrato cmos a due alimentazioni con un transistore mos integrato di protezione contro il <<latch-up>>.

Country Status (5)

Country Link
US (1) US4871927A (it)
JP (1) JPS63228663A (it)
DE (1) DE3806951C2 (it)
GB (1) GB2202403B (it)
IT (1) IT1217104B (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999761A (en) * 1985-10-01 1991-03-12 Maxim Integrated Products Integrated dual charge pump power supply and RS-232 transmitter/receiver
US5159204A (en) * 1987-11-18 1992-10-27 Bernacchi Jerald R Structure and method for preventing latch-up in integrated circuits
US5006737A (en) * 1989-04-24 1991-04-09 Motorola Inc. Transformerless semiconductor AC switch having internal biasing means
US5100821A (en) * 1989-04-24 1992-03-31 Motorola, Inc. Semiconductor AC switch
US5055903A (en) * 1989-06-22 1991-10-08 Siemens Aktiengesellschaft Circuit for reducing the latch-up sensitivity of a cmos circuit
FR2655196B1 (fr) * 1989-11-29 1992-04-10 Sgs Thomson Microelectronics Circuit d'isolation dynamique de circuits integres.
JP3128262B2 (ja) * 1991-05-28 2001-01-29 株式会社東芝 半導体集積回路装置
GB9115976D0 (en) * 1991-07-24 1991-11-06 Marconi Gec Ltd Protection of integrated circuit devices
JPH0554650A (ja) * 1991-08-26 1993-03-05 Nec Corp 半導体集積回路
US5444397A (en) * 1994-10-05 1995-08-22 Pericom Semiconductor Corp. All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages
US5563438A (en) * 1994-10-26 1996-10-08 Alliedsignal Inc. Rugged CMOS output stage design
TW451538B (en) * 1999-10-16 2001-08-21 Winbond Electronics Corp Latch up protection circuit suitable for use in multi power supply integrated circuit and its method
US6407898B1 (en) * 2000-01-18 2002-06-18 Taiwan Semiconductor Manufacturing Company Ltd. Protection means for preventing power-on sequence induced latch-up
US6329835B1 (en) 2000-02-23 2001-12-11 Pericom Semiconductor Corp. Quiet output buffers with neighbor sensing of wide bus and control signals
US6208178B1 (en) 2000-02-23 2001-03-27 Pericom Semiconductor Corp. CMOS over voltage-tolerant output buffer without transmission gate
US6452770B1 (en) * 2000-05-31 2002-09-17 Lucent Technologies Inc. Power buss inhibit through data input/output lines
TW490907B (en) * 2000-11-14 2002-06-11 Silicon Touch Tech Inc Circuit with protection for inverted connection of power source polarity
DE10315303B4 (de) 2003-04-02 2007-03-22 Infineon Technologies Ag Halbleiter-Bauelement-Spannungsversorgung für System mit mindestens zwei, insbesondere gestapelten, Halbleiter-Bauelementen
US7773442B2 (en) 2004-06-25 2010-08-10 Cypress Semiconductor Corporation Memory cell array latchup prevention
US9842629B2 (en) 2004-06-25 2017-12-12 Cypress Semiconductor Corporation Memory cell array latchup prevention
US7276957B2 (en) * 2005-09-30 2007-10-02 Agere Systems Inc. Floating well circuit having enhanced latch-up performance
DE102006000936B4 (de) 2006-01-05 2009-11-12 Infineon Technologies Ag Halbleiterbauelement mit Schutzschaltung gegen Lichtangriffe
US7355437B2 (en) * 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
CN104716936B (zh) * 2015-03-09 2017-09-22 广州金升阳科技有限公司 一种抗esd的信号解调集成电路
US10466732B2 (en) * 2018-03-28 2019-11-05 Richtek Technology Corporation Switching regulator and control circuit and control method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758351A (en) * 1980-09-24 1982-04-08 Toshiba Corp Substrate biasing device
US4559548A (en) * 1981-04-07 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha CMOS Charge pump free of parasitic injection
JPS6072256A (ja) * 1983-09-28 1985-04-24 Hitachi Ltd 半導体集積回路装置
JPS60231355A (ja) * 1984-04-27 1985-11-16 Mitsubishi Electric Corp 相補型半導体集積回路
US4670669A (en) * 1984-08-13 1987-06-02 International Business Machines Corporation Charge pumping structure for a substrate bias generator
JPS6167952A (ja) * 1984-09-11 1986-04-08 Nec Corp Ｃｍｏｓ半導体装置
US4647956A (en) * 1985-02-12 1987-03-03 Cypress Semiconductor Corp. Back biased CMOS device with means for eliminating latchup
JP2500802B2 (ja) * 1985-08-09 1996-05-29 株式会社 日立製作所 半導体装置
JPH05232689A (ja) * 1992-02-20 1993-09-10 Fujitsu Ltd ペリクル接着方法、ペリクル及びマスク

Also Published As

Publication number Publication date
GB8804099D0 (en) 1988-03-23
GB2202403A (en) 1988-09-21
IT8783609A0 (it) 1987-03-03
GB2202403B (en) 1991-07-31
DE3806951C2 (de) 1999-03-18
US4871927A (en) 1989-10-03
DE3806951A1 (de) 1988-09-15
JPS63228663A (ja) 1988-09-22

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329