US5130272A - Process for defining and forming an active region of very limited dimensions in a semiconductor layer - Google Patents

Process for defining and forming an active region of very limited dimensions in a semiconductor layer Download PDF

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Publication number
US5130272A
US5130272A US07/728,821 US72882191A US5130272A US 5130272 A US5130272 A US 5130272A US 72882191 A US72882191 A US 72882191A US 5130272 A US5130272 A US 5130272A
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United States
Prior art keywords
forming
mask
active region
semiconductor layer
layer
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Expired - Lifetime
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US07/728,821
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English (en)
Inventor
Giuseppe Ferla
Paolo Lanza
Carmelo Magro
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STMicroelectronics SRL
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SGS Thomson Microelectronics SRL
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/111—Narrow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Definitions

  • This invention relates to a process for defining and forming an active region of very limited dimensions in a semiconductor layer.
  • the manufacturing process of semiconductor devices requires defining and forming, one inside the other, active regions which differ for the type of dopant ("p" or "n") or for its concentration.
  • the process for defining and forming an active region of very limited dimensions within another active region of a semiconductor layer is according to the present invention, characterized by the following steps:
  • FIGS. 1-5 refer to an example of the known "spacers technology
  • FIGS. 6-14 refer to a first example of CS (Complementary Spacer) technology according to the present invention
  • FIG. 15 refers to a second example of CS technology according the present invention.
  • FIGS. 16-19 refer to a third example of a Power MOS obtained with CS technology
  • FIG. 20 refers to an example of a Power MOS obtained with CS technology
  • FIG. 21 refers to an example of a HIMOS device obtained with CS technology
  • FIG. 22 refers to an example of a lateral MOS transistor obtained with CS technology.
  • FIGS. 1, 2, 3, 4 and 5 illustrate an example of a known process for forming an active "long" region R2 within another "long” region R1 using the "spacer" technology.
  • a layer of silicon oxide SiO 2 or of polycrystalline silicon is deposited by CVD (Chemical Vapour Deposition) technology, the layer being of a thickness which is in a pre-established relation to the dimensions of the window to be obtained (the greater the thickness of layer 3, the wider the spacer obtained).
  • Layer 3 is than etched, using RIE (Reactive Ion Etching) technology, and a spacer 4 is consequently formed along the outline of the window of the previous photomasking (FIG. 3).
  • RIE reactive Ion Etching
  • the second region R2 is created by implantation or predeposition of a dopant and subsequent diffusion in the window outlined by the spacer (FIG. 4).
  • FIGS. 6 to 14 illustrate a first example of a process for defining and forming a "short" region inside a "long” region by CS technology according to the present invention.
  • the "short" region thus obtained using the CS technology is illustrated by the cross-sectional view of FIG. 3 and by the plan view of FIG. 14.
  • a thin layer 8 of silicon oxide (SiO 2 ) is prepared to act as a "pad” layer (to damp the stresses produced by the successive layers deposited by CVD) which is approximately 100-1000 Angstrom thick, as for example in FIG. 15.
  • SiO 2 silicon oxide
  • the spacer is removed in step 6 and not the pad oxide under the silicon nitride.
  • the "short" region is created by the following steps:
  • This variation is preferable when it is necessary to define very short regions, because by reducing the number of depositions it is possible to increase the precision in the dimensions.
  • Complementary Spacer by means of CVD deposition makes it possible to limit the uncertainty of the dimensions of the "short" region to a few hundred Angstrom;
  • the CS technology can be applied be pointed out that the CS technology can be applied in the manufacture of Power MOS (FIG. 20) and HIMOS (FIG. 21) devices.
  • the "long" region R1 constitutes the body
  • the “short” regions R2 represent the source
  • 2 constitutes the gate.
  • a further application is represented by lateral MOS transistors (FIG. 22) in which the "short" regions R'2 and R"2 represent, respectively, the source and the drain, while layer 12 of polysilicon, obtained by CVD deposition and subsequent photomasking, constitutes the gate.

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
US07/728,821 1989-07-24 1991-07-09 Process for defining and forming an active region of very limited dimensions in a semiconductor layer Expired - Lifetime US5130272A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT8921281A IT1231300B (it) 1989-07-24 1989-07-24 Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore
IT21281A/89 1989-07-24

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US07553956 Continuation 1990-07-17

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US5130272A true US5130272A (en) 1992-07-14

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US07/728,821 Expired - Lifetime US5130272A (en) 1989-07-24 1991-07-09 Process for defining and forming an active region of very limited dimensions in a semiconductor layer

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US (1) US5130272A (it)
EP (1) EP0410508A3 (it)
JP (1) JPH03141649A (it)
KR (1) KR910003750A (it)
IT (1) IT1231300B (it)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716859A (en) * 1995-12-22 1998-02-10 The Whitaker Corporation Method of fabricating a silicon BJT
US6090691A (en) * 1999-11-15 2000-07-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a raised source and drain without using selective epitaxial growth
US6214673B1 (en) * 1999-07-09 2001-04-10 Intersil Corporation Process for forming vertical semiconductor device having increased source contact area
US20040258977A1 (en) * 2003-01-24 2004-12-23 Hydrogenics Corporation Apparatus for and method of forming seals in fuel cells and fuel cell stacks

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3793721A (en) * 1971-08-02 1974-02-26 Texas Instruments Inc Integrated circuit and method of fabrication
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US4774198A (en) * 1986-03-06 1988-09-27 Sgs Microelettronica Spa Self-aligned process for fabricating small DMOS cells
US4879254A (en) * 1987-06-10 1989-11-07 Nippondenso Co., Ltd. Method of manufacturing a DMOS
US4960723A (en) * 1989-03-30 1990-10-02 Motorola, Inc. Process for making a self aligned vertical field effect transistor having an improved source contact

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4678537A (en) * 1985-05-23 1987-07-07 Sony Corporation Method of manufacturing semiconductor devices
DE3688057T2 (de) * 1986-01-10 1993-10-07 Gen Electric Halbleitervorrichtung und Methode zur Herstellung.
US4716126A (en) * 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3793721A (en) * 1971-08-02 1974-02-26 Texas Instruments Inc Integrated circuit and method of fabrication
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US4774198A (en) * 1986-03-06 1988-09-27 Sgs Microelettronica Spa Self-aligned process for fabricating small DMOS cells
US4879254A (en) * 1987-06-10 1989-11-07 Nippondenso Co., Ltd. Method of manufacturing a DMOS
US4960723A (en) * 1989-03-30 1990-10-02 Motorola, Inc. Process for making a self aligned vertical field effect transistor having an improved source contact

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716859A (en) * 1995-12-22 1998-02-10 The Whitaker Corporation Method of fabricating a silicon BJT
US6214673B1 (en) * 1999-07-09 2001-04-10 Intersil Corporation Process for forming vertical semiconductor device having increased source contact area
US6090691A (en) * 1999-11-15 2000-07-18 Chartered Semiconductor Manufacturing Ltd. Method for forming a raised source and drain without using selective epitaxial growth
US20040258977A1 (en) * 2003-01-24 2004-12-23 Hydrogenics Corporation Apparatus for and method of forming seals in fuel cells and fuel cell stacks

Also Published As

Publication number Publication date
IT8921281A0 (it) 1989-07-24
JPH03141649A (ja) 1991-06-17
EP0410508A2 (en) 1991-01-30
KR910003750A (ko) 1991-02-28
IT1231300B (it) 1991-11-28
EP0410508A3 (en) 1991-11-27

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