IT1240669B - Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom - Google Patents

Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom

Info

Publication number
IT1240669B
IT1240669B IT19507A IT1950790A IT1240669B IT 1240669 B IT1240669 B IT 1240669B IT 19507 A IT19507 A IT 19507A IT 1950790 A IT1950790 A IT 1950790A IT 1240669 B IT1240669 B IT 1240669B
Authority
IT
Italy
Prior art keywords
defining
current
memory cell
different levels
rom memory
Prior art date
Application number
IT19507A
Other languages
English (en)
Other versions
IT9019507A0 (it
IT9019507A1 (it
Inventor
Marco Olivo
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT19507A priority Critical patent/IT1240669B/it
Publication of IT9019507A0 publication Critical patent/IT9019507A0/it
Priority to EP91200360A priority patent/EP0448141A1/en
Publication of IT9019507A1 publication Critical patent/IT9019507A1/it
Application granted granted Critical
Publication of IT1240669B publication Critical patent/IT1240669B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
IT19507A 1990-02-27 1990-02-27 Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom IT1240669B (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT19507A IT1240669B (it) 1990-02-27 1990-02-27 Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom
EP91200360A EP0448141A1 (en) 1990-02-27 1991-02-20 Programming process suitable for defining at least four different current levels in an ROM memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT19507A IT1240669B (it) 1990-02-27 1990-02-27 Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom

Publications (3)

Publication Number Publication Date
IT9019507A0 IT9019507A0 (it) 1990-02-27
IT9019507A1 IT9019507A1 (it) 1991-08-27
IT1240669B true IT1240669B (it) 1993-12-17

Family

ID=11158609

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19507A IT1240669B (it) 1990-02-27 1990-02-27 Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom

Country Status (2)

Country Link
EP (1) EP0448141A1 (it)
IT (1) IT1240669B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0140691B1 (ko) * 1992-08-20 1998-06-01 문정환 반도체 장치의 마스크롬 제조방법
JP3256603B2 (ja) * 1993-07-05 2002-02-12 株式会社東芝 半導体装置及びその製造方法
JP3397427B2 (ja) * 1994-02-02 2003-04-14 株式会社東芝 半導体記憶装置
JPH07226446A (ja) * 1994-02-12 1995-08-22 Toshiba Corp 半導体装置及びその製造方法
US20040001355A1 (en) * 2002-06-27 2004-01-01 Matrix Semiconductor, Inc. Low-cost, serially-connected, multi-level mask-programmable read-only memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59148360A (ja) * 1983-02-14 1984-08-25 Fujitsu Ltd 半導体記憶装置及びその製造方法

Also Published As

Publication number Publication date
EP0448141A1 (en) 1991-09-25
IT9019507A0 (it) 1990-02-27
IT9019507A1 (it) 1991-08-27

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Legal Events

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