IT1255897B - Dispositivo a semiconduttore e procedimento per la sua fabbricazione - Google Patents
Dispositivo a semiconduttore e procedimento per la sua fabbricazioneInfo
- Publication number
- IT1255897B IT1255897B ITMI922403A ITMI922403A IT1255897B IT 1255897 B IT1255897 B IT 1255897B IT MI922403 A ITMI922403 A IT MI922403A IT MI922403 A ITMI922403 A IT MI922403A IT 1255897 B IT1255897 B IT 1255897B
- Authority
- IT
- Italy
- Prior art keywords
- type
- concentration
- well
- peaks
- impurities
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Una zona profonda o "well" (5) di tipo n e un well (6) di tipo p sono formati in un substrato (1) di silicio. Il well (5) di tipo n a picchi (51, 52) e (53a) di concentrazione di impurità di tipo n e un picco (53b) di concentrazione di impurità di tipo p. Il well (6) di tipo p ha picchi (61, 62) e (63) di concentrazione di tipo p. I picchi (51) e (61) di concentrazione di impurità serventi come regioni di arresto di canale per isolare elementi esistono solamente in prossimità della superficie inferiore di una pellicola d'ossido isolante (2) ma non in regioni di elementi.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27414291 | 1991-10-22 | ||
| JP4195567A JP2851753B2 (ja) | 1991-10-22 | 1992-07-22 | 半導体装置およびその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI922403A0 ITMI922403A0 (it) | 1992-10-20 |
| ITMI922403A1 ITMI922403A1 (it) | 1994-04-20 |
| IT1255897B true IT1255897B (it) | 1995-11-17 |
Family
ID=26509207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI922403A IT1255897B (it) | 1991-10-22 | 1992-10-20 | Dispositivo a semiconduttore e procedimento per la sua fabbricazione |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5763921A (it) |
| JP (1) | JP2851753B2 (it) |
| DE (1) | DE4233236C2 (it) |
| IT (1) | IT1255897B (it) |
Families Citing this family (63)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07201974A (ja) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP3386101B2 (ja) * | 1996-08-29 | 2003-03-17 | シャープ株式会社 | 半導体装置の製造方法 |
| US6417550B1 (en) * | 1996-08-30 | 2002-07-09 | Altera Corporation | High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage |
| US6107672A (en) * | 1997-09-04 | 2000-08-22 | Matsushita Electronics Corporation | Semiconductor device having a plurality of buried wells |
| JP3340361B2 (ja) * | 1997-10-01 | 2002-11-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP4931267B2 (ja) | 1998-01-29 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US6137148A (en) * | 1998-06-26 | 2000-10-24 | Elmos Semiconductor Ag | NMOS transistor |
| KR100324931B1 (ko) | 1999-01-22 | 2002-02-28 | 박종섭 | 반도체장치 및 그의 제조방법 |
| US7064399B2 (en) | 2000-09-15 | 2006-06-20 | Texas Instruments Incorporated | Advanced CMOS using super steep retrograde wells |
| KR100489693B1 (ko) * | 2001-02-16 | 2005-05-17 | 인티그런트 테크놀로지즈(주) | 선형성이 향상된 증폭 회로 및 믹서 회로 |
| US6833297B1 (en) * | 2002-10-04 | 2004-12-21 | Advanced Micro Devices, Inc. | Method for reducing drain induced barrier lowering in a memory device |
| US7303949B2 (en) | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
| JP4540438B2 (ja) * | 2004-09-27 | 2010-09-08 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| JP2007073578A (ja) * | 2005-09-05 | 2007-03-22 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
| US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
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| US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
| US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
| US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
| US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
| US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
| US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
| US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
| US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
| US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
| US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
| US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
| US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
| US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
| WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
| US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
| US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
| US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
| US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
| US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
| US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
| US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
| US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
| US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
| US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
| US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
| US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
| US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
| US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
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| US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
| US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
| US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
| CN104854698A (zh) | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | 具有低变化晶体管外围电路的dram型器件以及相关方法 |
| US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
| US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
| US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
| US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
| US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
| US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
| US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
| US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
| JP6242678B2 (ja) * | 2013-12-25 | 2017-12-06 | 住友化学株式会社 | 窒化物半導体素子及びその製造方法 |
| US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
| US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4506436A (en) * | 1981-12-21 | 1985-03-26 | International Business Machines Corporation | Method for increasing the radiation resistance of charge storage semiconductor devices |
| FR2577339B1 (fr) * | 1985-02-12 | 1991-05-10 | Eurotechnique Sa | Memoire dynamique en circuit integre |
| NL8501838A (nl) * | 1985-06-26 | 1987-01-16 | Stork Friesland Bv | Semi-permeabele membranen op basis van sulfonaat-groepen bevattende polymeren. |
| NL8501992A (nl) * | 1985-07-11 | 1987-02-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
| JP2634163B2 (ja) * | 1987-02-19 | 1997-07-23 | 三菱電機株式会社 | 半導体記憶装置 |
| JPH06105774B2 (ja) * | 1987-11-17 | 1994-12-21 | 富士通株式会社 | 半導体記憶装置及びその製造方法 |
| JP2745228B2 (ja) * | 1989-04-05 | 1998-04-28 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JPH02276274A (ja) * | 1989-04-18 | 1990-11-13 | Matsushita Electron Corp | 半導体装置の製造方法 |
| JP2965783B2 (ja) * | 1991-07-17 | 1999-10-18 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
-
1992
- 1992-07-22 JP JP4195567A patent/JP2851753B2/ja not_active Expired - Lifetime
- 1992-10-02 DE DE4233236A patent/DE4233236C2/de not_active Expired - Fee Related
- 1992-10-20 IT ITMI922403A patent/IT1255897B/it active IP Right Grant
-
1996
- 1996-05-14 US US08/645,700 patent/US5763921A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE4233236C2 (de) | 1995-09-14 |
| US5763921A (en) | 1998-06-09 |
| ITMI922403A0 (it) | 1992-10-20 |
| JP2851753B2 (ja) | 1999-01-27 |
| ITMI922403A1 (it) | 1994-04-20 |
| DE4233236A1 (de) | 1993-04-29 |
| JPH05190781A (ja) | 1993-07-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19971030 |