IT1255933B - Circuito di ridonanza di colonna per un dispositivo di memoria a semiconduttore. - Google Patents
Circuito di ridonanza di colonna per un dispositivo di memoria a semiconduttore.Info
- Publication number
- IT1255933B IT1255933B ITMI922474A ITMI922474A IT1255933B IT 1255933 B IT1255933 B IT 1255933B IT MI922474 A ITMI922474 A IT MI922474A IT MI922474 A ITMI922474 A IT MI922474A IT 1255933 B IT1255933 B IT 1255933B
- Authority
- IT
- Italy
- Prior art keywords
- control circuit
- fuse
- column
- receiving
- memory device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000003068 static effect Effects 0.000 abstract 3
- 239000011159 matrix material Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Un dispositivo di memoria a semiconduttore comprende un circuito di ridondanza di colonna includente un circuito di controllo ridondante di colonna per la ricezione di un segnale di indirizzo di riga e un blocco fusibili per la ricezione del segnale di uscita del circuito di controllo ridondante di colonna ed un circuito di controllo di selezione di blocco con un ingresso per ricevere il segnale di uscita del circuito di controllo ridondante di colonna ed una uscita connessa con la pluralità di circuiti a fusibile, il circuito di controllo di selezione comprendendo una pluralità di circuiti a fusibile ognuno avente almeno un fusibile connesso ad una data tensione statica, per cui una delle colonne connessa con una normale linea di selezione di colonna che si guasta è sostituita da una delle colonne di una matrice di celle di ricambio sotto la funzione di riparazione del circuito di controllo della selezione del blocco. La tensione statica è una tensione sorgente fornita al chip. La tensione statica data è per rendere inefficace uno specifico ingresso di segnale di indirizzo ai circuiti e fusibile.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920007621A KR950000275B1 (ko) | 1992-05-06 | 1992-05-06 | 반도체 메모리 장치의 컬럼 리던던시 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI922474A0 ITMI922474A0 (it) | 1992-10-28 |
| ITMI922474A1 ITMI922474A1 (it) | 1994-04-28 |
| IT1255933B true IT1255933B (it) | 1995-11-17 |
Family
ID=19332732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI922474A IT1255933B (it) | 1992-05-06 | 1992-10-28 | Circuito di ridonanza di colonna per un dispositivo di memoria a semiconduttore. |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5325334A (it) |
| JP (1) | JP2555252B2 (it) |
| KR (1) | KR950000275B1 (it) |
| DE (1) | DE4236099C2 (it) |
| FR (1) | FR2691000B1 (it) |
| GB (1) | GB2266795B (it) |
| IT (1) | IT1255933B (it) |
| TW (1) | TW296838U (it) |
Families Citing this family (61)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05334895A (ja) * | 1992-05-28 | 1993-12-17 | Texas Instr Japan Ltd | 半導体記憶装置 |
| US5469401A (en) * | 1992-07-14 | 1995-11-21 | Mosaid Technologies Incorporated | Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address |
| KR0119888B1 (ko) * | 1994-04-11 | 1997-10-30 | 윤종용 | 반도체 메모리장치의 결함구제방법 및 그 회로 |
| KR0131721B1 (ko) * | 1994-06-08 | 1998-04-15 | 김주용 | 반도체 소자의 컬럼 리던던시 장치 |
| KR0130030B1 (ko) * | 1994-08-25 | 1998-10-01 | 김광호 | 반도체 메모리 장치의 컬럼 리던던시 회로 및 그 방법 |
| US5528539A (en) * | 1994-09-29 | 1996-06-18 | Micron Semiconductor, Inc. | High speed global row redundancy system |
| US5805512A (en) * | 1995-02-09 | 1998-09-08 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US5838620A (en) * | 1995-04-05 | 1998-11-17 | Micron Technology, Inc. | Circuit for cancelling and replacing redundant elements |
| KR0157344B1 (ko) * | 1995-05-25 | 1998-12-01 | 김광호 | 반도체 메모리 장치의 퓨즈소자 회로 |
| KR100217910B1 (ko) * | 1995-08-17 | 1999-09-01 | 김영환 | 플래쉬 메모리셀의 리페어 회로 및 리페어 방법 |
| US5592102A (en) * | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
| US5812468A (en) * | 1995-11-28 | 1998-09-22 | Micron Technology, Inc. | Programmable device for redundant element cancel in a memory |
| US5828599A (en) * | 1996-08-06 | 1998-10-27 | Simtek Corporation | Memory with electrically erasable and programmable redundancy |
| KR100450115B1 (ko) * | 1996-11-08 | 2004-11-26 | 주식회사 하이닉스반도체 | 반도체메모리장치의컬럼리던던시회로 |
| US5996096A (en) * | 1996-11-15 | 1999-11-30 | International Business Machines Corporation | Dynamic redundancy for random access memory assemblies |
| US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
| US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
| US5912579A (en) * | 1997-02-06 | 1999-06-15 | Zagar; Paul S. | Circuit for cancelling and replacing redundant elements |
| CA2202692C (en) * | 1997-04-14 | 2006-06-13 | Mosaid Technologies Incorporated | Column redundancy in semiconductor memories |
| EP0983549B1 (en) * | 1997-05-23 | 2001-12-12 | Altera Corporation (a Delaware Corporation) | Redundancy circuitry for programmable logic devices with interleaved input circuits |
| US6055611A (en) * | 1997-07-09 | 2000-04-25 | Micron Technology, Inc. | Method and apparatus for enabling redundant memory |
| US5999463A (en) * | 1997-07-21 | 1999-12-07 | Samsung Electronics Co., Ltd. | Redundancy fuse box and semiconductor device including column redundancy fuse box shared by a plurality of memory blocks |
| US5896331A (en) * | 1997-12-23 | 1999-04-20 | Lsi Logic Corporation | Reprogrammable addressing process for embedded DRAM |
| US5907511A (en) * | 1997-12-23 | 1999-05-25 | Lsi Logic Corporation | Electrically selectable redundant components for an embedded DRAM |
| US5901095A (en) * | 1997-12-23 | 1999-05-04 | Lsi Logic Corporation | Reprogrammable address selector for an embedded DRAM |
| US6011734A (en) * | 1998-03-12 | 2000-01-04 | Motorola, Inc. | Fuseless memory repair system and method of operation |
| US5999440A (en) * | 1998-03-30 | 1999-12-07 | Lsi Logic Corporation | Embedded DRAM with noise-protecting substrate isolation well |
| US6064588A (en) * | 1998-03-30 | 2000-05-16 | Lsi Logic Corporation | Embedded dram with noise-protected differential capacitor memory cells |
| US5978304A (en) * | 1998-06-30 | 1999-11-02 | Lsi Logic Corporation | Hierarchical, adaptable-configuration dynamic random access memory |
| US6005824A (en) * | 1998-06-30 | 1999-12-21 | Lsi Logic Corporation | Inherently compensated clocking circuit for dynamic random access memory |
| US6987786B2 (en) | 1998-07-02 | 2006-01-17 | Gsi Group Corporation | Controlling laser polarization |
| US6181728B1 (en) | 1998-07-02 | 2001-01-30 | General Scanning, Inc. | Controlling laser polarization |
| US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
| US5953269A (en) * | 1998-09-03 | 1999-09-14 | Micron Technology, Inc. | Method and apparatus for remapping addresses for redundancy |
| KR100304700B1 (ko) | 1999-01-13 | 2001-09-26 | 윤종용 | 버퍼부를 내장하여 부하를 일정하게 하는 리던던시 회로 |
| KR100370232B1 (ko) | 1999-04-28 | 2003-01-29 | 삼성전자 주식회사 | 결함 셀을 리던던시 셀로의 대체를 반복 수행할 수 있는 리던던시 회로 |
| US6101138A (en) * | 1999-07-22 | 2000-08-08 | Eton Technology, Inc. | Area efficient global row redundancy scheme for DRAM |
| KR100363089B1 (ko) * | 1999-09-07 | 2002-11-30 | 삼성전자 주식회사 | 리던던시 효율을 향상시키는 리던던시 회로를 포함하는반도체 메모리 장치 |
| KR100363085B1 (ko) * | 1999-11-05 | 2002-12-05 | 삼성전자 주식회사 | 리던던시 효율을 향상시키는 로우 리던던시 스킴을 갖는반도체장치 |
| KR100337476B1 (ko) | 2000-03-17 | 2002-05-23 | 윤종용 | 반도체 메모리 장치 및 이 장치의 리던던시 회로 및 방법 |
| KR100351902B1 (ko) * | 2000-09-28 | 2002-09-12 | 주식회사 하이닉스반도체 | 칼럼 리던던시 리페어 회로 |
| TW546664B (en) * | 2001-01-17 | 2003-08-11 | Toshiba Corp | Semiconductor storage device formed to optimize test technique and redundancy technology |
| US6400619B1 (en) | 2001-04-25 | 2002-06-04 | International Business Machines Corporation | Micro-cell redundancy scheme for high performance eDRAM |
| KR100408714B1 (ko) * | 2001-06-28 | 2003-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 컬럼 리페어회로 및 방법 |
| DE10152086B4 (de) * | 2001-10-23 | 2007-03-22 | Infineon Technologies Ag | Verfahren zum Testen einer Mehrzahl von Bauelementen auf einem Wafer mit einer gemeinsamen Datenleitung und einer gemeinsamen Versorgungsleitung |
| US6801471B2 (en) * | 2002-02-19 | 2004-10-05 | Infineon Technologies Ag | Fuse concept and method of operation |
| US7093156B1 (en) * | 2002-05-13 | 2006-08-15 | Virage Logic Corp. | Embedded test and repair scheme and interface for compiling a memory assembly with redundancy implementation |
| US7159141B2 (en) * | 2002-07-01 | 2007-01-02 | Micron Technology, Inc. | Repairable block redundancy scheme |
| KR100542696B1 (ko) * | 2003-11-13 | 2006-01-11 | 주식회사 하이닉스반도체 | 반도체 장치의 리페어 퓨즈 박스 |
| US8072834B2 (en) | 2005-08-25 | 2011-12-06 | Cypress Semiconductor Corporation | Line driver circuit and method with standby mode of operation |
| KR100827659B1 (ko) * | 2006-09-20 | 2008-05-07 | 삼성전자주식회사 | 반도체 메모리 장치 |
| JP2009087513A (ja) * | 2007-10-03 | 2009-04-23 | Nec Electronics Corp | 半導体記憶装置、及びメモリセルテスト方法 |
| US8976604B2 (en) | 2012-02-13 | 2015-03-10 | Macronix International Co., Lt. | Method and apparatus for copying data with a memory array having redundant memory |
| US9165680B2 (en) | 2013-03-11 | 2015-10-20 | Macronix International Co., Ltd. | Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks |
| KR20150123378A (ko) * | 2014-04-24 | 2015-11-04 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 동작 방법 |
| US9773571B2 (en) | 2014-12-16 | 2017-09-26 | Macronix International Co., Ltd. | Memory repair redundancy with array cache redundancy |
| US20160218286A1 (en) | 2015-01-23 | 2016-07-28 | Macronix International Co., Ltd. | Capped contact structure with variable adhesion layer thickness |
| US9514815B1 (en) | 2015-05-13 | 2016-12-06 | Macronix International Co., Ltd. | Verify scheme for ReRAM |
| US9691478B1 (en) | 2016-04-22 | 2017-06-27 | Macronix International Co., Ltd. | ReRAM array configuration for bipolar operation |
| KR102597291B1 (ko) * | 2016-11-07 | 2023-11-06 | 에스케이하이닉스 주식회사 | 리페어 제어 장치 및 이를 포함하는 반도체 장치 |
| US9959928B1 (en) | 2016-12-13 | 2018-05-01 | Macronix International Co., Ltd. | Iterative method and apparatus to program a programmable resistance memory element using stabilizing pulses |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2154032B (en) * | 1984-02-08 | 1988-04-20 | Inmos Ltd | A repairable memory array |
| US4758993A (en) * | 1984-11-19 | 1988-07-19 | Fujitsu Limited | Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays |
| US4827747A (en) * | 1986-05-21 | 1989-05-09 | Hitachi, Ltd. | Method for producing a bellows with oval cross section and apparatus for carrying out the method |
| KR890003691B1 (ko) * | 1986-08-22 | 1989-09-30 | 삼성전자 주식회사 | 블럭 열 리던던씨 회로 |
| US5193076A (en) * | 1988-12-22 | 1993-03-09 | Texas Instruments Incorporated | Control of sense amplifier latch timing |
| NL8900026A (nl) * | 1989-01-06 | 1990-08-01 | Philips Nv | Matrixgeheugen, bevattende standaardblokken, standaardsubblokken, een redundant blok, en redundante subblokken, alsmede geintegreerde schakeling bevattende meerdere van zulke matrixgeheugens. |
| KR910005601B1 (ko) * | 1989-05-24 | 1991-07-31 | 삼성전자주식회사 | 리던던트 블럭을 가지는 반도체 메모리장치 |
| KR920010347B1 (ko) * | 1989-12-30 | 1992-11-27 | 삼성전자주식회사 | 분할된 워드라인을 가지는 메모리장치의 리던던시 구조 |
| KR930001793B1 (en) * | 1989-12-30 | 1993-03-13 | Korea Telecommunication | Main-c.p.u. watching apparatus |
| DE69128173T2 (de) * | 1990-07-31 | 1998-05-14 | Texas Instruments Inc | Redundante Halbleiterspeicheranordnung |
| US5210723A (en) * | 1990-10-31 | 1993-05-11 | International Business Machines Corporation | Memory with page mode |
| US5159572A (en) * | 1990-12-24 | 1992-10-27 | Motorola, Inc. | DRAM architecture having distributed address decoding and timing control |
| KR930003164A (ko) * | 1991-07-26 | 1993-02-24 | 김광호 | 반도체메모리 리던던시 장치 |
| US5257229A (en) * | 1992-01-31 | 1993-10-26 | Sgs-Thomson Microelectronics, Inc. | Column redundancy architecture for a read/write memory |
-
1992
- 1992-05-06 KR KR1019920007621A patent/KR950000275B1/ko not_active Expired - Fee Related
- 1992-10-03 TW TW083215092U patent/TW296838U/zh unknown
- 1992-10-22 FR FR9212658A patent/FR2691000B1/fr not_active Expired - Lifetime
- 1992-10-26 DE DE4236099A patent/DE4236099C2/de not_active Expired - Lifetime
- 1992-10-28 IT ITMI922474A patent/IT1255933B/it active IP Right Grant
- 1992-10-30 JP JP4292914A patent/JP2555252B2/ja not_active Expired - Fee Related
- 1992-11-02 GB GB9222905A patent/GB2266795B/en not_active Expired - Lifetime
-
1993
- 1993-02-05 US US08/014,305 patent/US5325334A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE4236099A1 (de) | 1993-11-11 |
| US5325334A (en) | 1994-06-28 |
| ITMI922474A1 (it) | 1994-04-28 |
| JP2555252B2 (ja) | 1996-11-20 |
| KR930024021A (ko) | 1993-12-21 |
| TW296838U (en) | 1997-01-21 |
| GB2266795B (en) | 1996-06-05 |
| GB2266795A (en) | 1993-11-10 |
| FR2691000B1 (fr) | 1996-05-24 |
| JPH0660690A (ja) | 1994-03-04 |
| FR2691000A1 (fr) | 1993-11-12 |
| GB9222905D0 (en) | 1992-12-16 |
| KR950000275B1 (ko) | 1995-01-12 |
| ITMI922474A0 (it) | 1992-10-28 |
| DE4236099C2 (de) | 2001-01-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19971028 |