IT1259563B - Metodo per la fabbricazione di un dispositivo cmos a doppio pozzetto - Google Patents

Metodo per la fabbricazione di un dispositivo cmos a doppio pozzetto

Info

Publication number
IT1259563B
IT1259563B ITTO920366A ITTO920366A IT1259563B IT 1259563 B IT1259563 B IT 1259563B IT TO920366 A ITTO920366 A IT TO920366A IT TO920366 A ITTO920366 A IT TO920366A IT 1259563 B IT1259563 B IT 1259563B
Authority
IT
Italy
Prior art keywords
layer
oxide layer
photoinhibitor
silicon substrate
portions
Prior art date
Application number
ITTO920366A
Other languages
English (en)
Inventor
Dai Hoon Lee
Hyung Lim Ji
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Publication of ITTO920366A0 publication Critical patent/ITTO920366A0/it
Publication of ITTO920366A1 publication Critical patent/ITTO920366A1/it
Application granted granted Critical
Publication of IT1259563B publication Critical patent/IT1259563B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Viene descritto un metodo per la fabbricazione di un dispositivo semiconduttore CMOS avente pozzetti doppi. Viene provvisto dapprima un substrato di silicio. Viene depositato uno spesso strato di ossido e un primo strato di fotoinibitore viene applicato in successione sul substrato di silicio. Successivamente viene formato un tracciato di maschera del pozzetto N rimuovendo una porzione del primo strato di fotoinibitore, così da definire una regione di chiave di allineamento e una regione di pozzetto N e formando un sottile strato di ossido su tali regioni. Viene quindi attuato un procedimento di impianto di impurezza di tipo N attraverso porzioni esposte del sottile strato di ossido nel substrato di silicio, e vengono rimosse le prime porzioni dello strato di fotoinibitore rimanenti sullo strato spesso di ossido, così da esporre tutta la superficie dello spesso strato di ossido. Successivamente viene formato un tracciato di maschera di pozzetto P rimuovendo porzioni del secondo strato di fotoinibitore, così da definire una regione di pozzetto P e da formare su questa un sottile strato di ossido. Si effettua un processo di diffusione di impurezza di tipo P attraverso porzioni esposte del sottile strato di ossido entro il substrato di silicio, e vengono rimosse le porzioni rimanenti del secondo strato di fotoinibitore. Successivamente vengono formate una regione di pozzetto N e una regione di pozzetto P nel substrato mediante un processo di ridistribuzione, e vengono rimossi uno stato di ossido cresciuto sopra e sotto il sottile strato di ossido e lo strato di ossido spesso.
ITTO920366A 1991-05-03 1992-04-28 Metodo per la fabbricazione di un dispositivo cmos a doppio pozzetto IT1259563B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910007187A KR940009997B1 (ko) 1991-05-03 1991-05-03 Cmos의 단차없는 두개의 웰 제조방법

Publications (3)

Publication Number Publication Date
ITTO920366A0 ITTO920366A0 (it) 1992-04-28
ITTO920366A1 ITTO920366A1 (it) 1993-10-28
IT1259563B true IT1259563B (it) 1996-03-20

Family

ID=19314068

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO920366A IT1259563B (it) 1991-05-03 1992-04-28 Metodo per la fabbricazione di un dispositivo cmos a doppio pozzetto

Country Status (4)

Country Link
US (1) US5252510A (it)
JP (1) JP2521611B2 (it)
KR (1) KR940009997B1 (it)
IT (1) IT1259563B (it)

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JP3174786B2 (ja) * 1991-05-31 2001-06-11 富士通株式会社 半導体装置の製造方法
JP3404873B2 (ja) * 1994-03-25 2003-05-12 株式会社デンソー 半導体装置の製造方法
TW322629B (en) * 1996-09-06 1997-12-11 Holtek Microelectronics Inc Manufacturing method of integrated circuit alignment mark
TW311273B (en) * 1996-09-26 1997-07-21 Holtek Microelectronics Inc Manufacturing method of high step alignment mark
US5776816A (en) * 1996-10-28 1998-07-07 Holtek Microelectronics, Inc. Nitride double etching for twin well align
US5688710A (en) * 1996-11-27 1997-11-18 Holtek Microelectronics, Inc. Method of fabricating a twin - well CMOS device
KR100266652B1 (ko) * 1997-12-29 2000-11-01 김영환 반도체 소자의 트윈 웰 형성방법
US6133077A (en) 1998-01-13 2000-10-17 Lsi Logic Corporation Formation of high-voltage and low-voltage devices on a semiconductor substrate
US6093585A (en) * 1998-05-08 2000-07-25 Lsi Logic Corporation High voltage tolerant thin film transistor
KR100554201B1 (ko) * 1999-03-29 2006-02-22 페어차일드코리아반도체 주식회사 씨디모스 제조방법
US6573151B1 (en) * 2000-08-22 2003-06-03 Advanced Micro Devices, Inc. Method of forming zero marks
KR100450566B1 (ko) * 2001-12-24 2004-09-30 동부전자 주식회사 씨모오스형 트랜지스터 제조 방법
KR100480593B1 (ko) * 2002-01-04 2005-04-06 삼성전자주식회사 활성 영역 한정용 얼라인 키를 가지는 반도체 소자 및 그제조 방법
US6596604B1 (en) * 2002-07-22 2003-07-22 Atmel Corporation Method of preventing shift of alignment marks during rapid thermal processing
KR100515057B1 (ko) * 2003-01-10 2005-09-14 삼성전자주식회사 반도체 소자의 트렌치 소자분리막들 형성방법
US7435659B2 (en) * 2005-02-28 2008-10-14 Texas Instruments Incorporated Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process
JP3775508B1 (ja) * 2005-03-10 2006-05-17 株式会社リコー 半導体装置の製造方法及び半導体装置
JP4718961B2 (ja) * 2005-09-30 2011-07-06 株式会社東芝 半導体集積回路装置及びその製造方法
KR100734325B1 (ko) * 2006-07-14 2007-07-02 삼성전자주식회사 반도체 소자의 제조방법
KR100850121B1 (ko) * 2006-10-19 2008-08-04 동부일렉트로닉스 주식회사 얼라인 키를 이용한 반도체 소자의 웰 제조 방법
CN116721992A (zh) * 2023-07-18 2023-09-08 江苏帝奥微电子股份有限公司 一种高速开关通道结构及制备工艺

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JPH01241158A (ja) * 1988-03-23 1989-09-26 Toshiba Corp 半導体集積回路の製造方法
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JPH0377377A (ja) * 1989-08-19 1991-04-02 Mitsubishi Electric Corp 半導体装置の製造方法
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Also Published As

Publication number Publication date
KR920022383A (ko) 1992-12-19
ITTO920366A0 (it) 1992-04-28
US5252510A (en) 1993-10-12
JP2521611B2 (ja) 1996-08-07
KR940009997B1 (ko) 1994-10-19
JPH05160355A (ja) 1993-06-25
ITTO920366A1 (it) 1993-10-28

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429