IT8021316A0 - Memoria mosfet ad accesso casuale ad alta densita'. - Google Patents

Memoria mosfet ad accesso casuale ad alta densita'.

Info

Publication number
IT8021316A0
IT8021316A0 IT8021316A IT2131680A IT8021316A0 IT 8021316 A0 IT8021316 A0 IT 8021316A0 IT 8021316 A IT8021316 A IT 8021316A IT 2131680 A IT2131680 A IT 2131680A IT 8021316 A0 IT8021316 A0 IT 8021316A0
Authority
IT
Italy
Prior art keywords
random access
high density
mosfet memory
density random
access mosfet
Prior art date
Application number
IT8021316A
Other languages
English (en)
Other versions
IT1149830B (it
Inventor
Tze Ho Irving
Riseman Jacob
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8021316A0 publication Critical patent/IT8021316A0/it
Application granted granted Critical
Publication of IT1149830B publication Critical patent/IT1149830B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
IT21316/80A 1979-05-07 1980-04-11 Memoria mosfet ad accesso casuale ad alta densita' IT1149830B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/036,722 US4252579A (en) 1979-05-07 1979-05-07 Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition

Publications (2)

Publication Number Publication Date
IT8021316A0 true IT8021316A0 (it) 1980-04-11
IT1149830B IT1149830B (it) 1986-12-10

Family

ID=21890246

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21316/80A IT1149830B (it) 1979-05-07 1980-04-11 Memoria mosfet ad accesso casuale ad alta densita'

Country Status (6)

Country Link
US (1) US4252579A (it)
EP (1) EP0018501B1 (it)
JP (1) JPS5840343B2 (it)
CA (1) CA1133136A (it)
DE (1) DE3063421D1 (it)
IT (1) IT1149830B (it)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827667B2 (ja) * 1979-02-19 1983-06-10 富士通株式会社 半導体装置
JPS5636143A (en) * 1979-08-31 1981-04-09 Hitachi Ltd Manufacture of semiconductor device
US4333227A (en) * 1979-11-29 1982-06-08 International Business Machines Corporation Process for fabricating a self-aligned micrometer bipolar transistor device
US4400715A (en) * 1980-11-19 1983-08-23 International Business Machines Corporation Thin film semiconductor device and method for manufacture
US4333794A (en) * 1981-04-07 1982-06-08 International Business Machines Corporation Omission of thick Si3 N4 layers in ISA schemes
GB2104722B (en) * 1981-06-25 1985-04-24 Suwa Seikosha Kk Mos semiconductor device and method of manufacturing the same
JPS583248A (ja) * 1981-06-30 1983-01-10 Toshiba Corp バイポ−ラ型半導体装置の製造方法
US4375124A (en) * 1981-11-12 1983-03-01 Gte Laboratories Incorporated Power static induction transistor fabrication
US4554570A (en) * 1982-06-24 1985-11-19 Rca Corporation Vertically integrated IGFET device
JPS5982761A (ja) * 1982-11-04 1984-05-12 Hitachi Ltd 半導体メモリ
US4830975A (en) * 1983-01-13 1989-05-16 National Semiconductor Corporation Method of manufacture a primos device
JPH0666436B2 (ja) * 1983-04-15 1994-08-24 株式会社日立製作所 半導体集積回路装置
JPS6070766A (ja) * 1983-09-26 1985-04-22 Mitsubishi Electric Corp 半導体装置の製造方法
JPS60128654A (ja) * 1983-12-16 1985-07-09 Hitachi Ltd 半導体集積回路
JPH0793365B2 (ja) * 1984-09-11 1995-10-09 株式会社東芝 半導体記憶装置およびその製造方法
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US4916511A (en) * 1985-05-03 1990-04-10 Texas Instruments Incorporated Trench structure and process
US4788158A (en) * 1985-09-25 1988-11-29 Texas Instruments Incorporated Method of making vertical inverter
US4937648A (en) * 1986-03-12 1990-06-26 Huang Jack S T Resistant transistor
NL8600786A (nl) * 1986-03-27 1987-10-16 Philips Nv Ladingsgekoppelde inrichting.
US4829017A (en) * 1986-09-25 1989-05-09 Texas Instruments Incorporated Method for lubricating a high capacity dram cell
JPS6370851U (it) * 1986-10-28 1988-05-12
US5082795A (en) * 1986-12-05 1992-01-21 General Electric Company Method of fabricating a field effect semiconductor device having a self-aligned structure
US4794561A (en) * 1987-07-02 1988-12-27 Integrated Device Technology, Inc. Static ram cell with trench pull-down transistors and buried-layer ground plate
US5545290A (en) * 1987-07-09 1996-08-13 Texas Instruments Incorporated Etching method
US5164325A (en) * 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
US5015594A (en) * 1988-10-24 1991-05-14 International Business Machines Corporation Process of making BiCMOS devices having closely spaced device regions
US4894697A (en) * 1988-10-31 1990-01-16 International Business Machines Corporation Ultra dense dram cell and its method of fabrication
US5028980A (en) * 1988-12-21 1991-07-02 Texas Instruments Incorporated Trench capacitor with expanded area
US5064777A (en) * 1990-06-28 1991-11-12 International Business Machines Corporation Fabrication method for a double trench memory cell device
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5395784A (en) * 1993-04-14 1995-03-07 Industrial Technology Research Institute Method of manufacturing low leakage and long retention time DRAM
KR0123751B1 (ko) 1993-10-07 1997-11-25 김광호 반도체장치 및 그 제조방법
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
US6066869A (en) * 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5907170A (en) 1997-10-06 1999-05-25 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US6528837B2 (en) 1997-10-06 2003-03-04 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
KR100275727B1 (ko) 1998-01-06 2001-01-15 윤종용 반도체 장치의 커패시터 형성방법
US6025225A (en) * 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
US6246083B1 (en) 1998-02-24 2001-06-12 Micron Technology, Inc. Vertical gain cell and array for a dynamic random access memory
US6124729A (en) 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
US5991225A (en) * 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6043527A (en) 1998-04-14 2000-03-28 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
US6208164B1 (en) 1998-08-04 2001-03-27 Micron Technology, Inc. Programmable logic array with vertical transistors
US6134175A (en) 1998-08-04 2000-10-17 Micron Technology, Inc. Memory address decode array with vertical transistors
US7229872B2 (en) * 2000-04-04 2007-06-12 International Rectifier Corporation Low voltage power MOSFET device and process for its manufacture
SG112804A1 (en) * 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
JP2007189008A (ja) * 2006-01-12 2007-07-26 Elpida Memory Inc 半導体記憶装置およびその製造方法
US10361200B1 (en) 2018-03-07 2019-07-23 International Business Machines Corporation Vertical fin field effect transistor with integral U-shaped electrical gate connection
US20230292497A1 (en) * 2022-03-11 2023-09-14 Nanya Technology Corporation Manufacturing method of semiconductor structure

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3412297A (en) * 1965-12-16 1968-11-19 United Aircraft Corp Mos field-effect transistor with a onemicron vertical channel
US4017883A (en) * 1971-07-06 1977-04-12 Ibm Corporation Single-electrode charge-coupled random access memory cell with impurity implanted gate region
US3938241A (en) * 1972-10-24 1976-02-17 Motorola, Inc. Vertical channel junction field-effect transistors and method of manufacture
NL157137B (nl) * 1973-03-27 1978-06-15 Nkf Kabel Bv Werkwijze en inrichting voor het gelijkmatig met poedervormig materiaal bedekken van een langwerpig voorwerp, waarvan althans de buitenlaag bestaat uit door warmte smeltbare kunststof.
US3975221A (en) * 1973-08-29 1976-08-17 American Micro-Systems, Inc. Low capacitance V groove MOS NOR gate and method of manufacture
US4003126A (en) * 1974-09-12 1977-01-18 Canadian Patents And Development Limited Method of making metal oxide semiconductor devices
US4037306A (en) * 1975-10-02 1977-07-26 Motorola, Inc. Integrated circuit and method
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element
US4222062A (en) * 1976-05-04 1980-09-09 American Microsystems, Inc. VMOS Floating gate memory device
US4070690A (en) * 1976-08-17 1978-01-24 Westinghouse Electric Corporation VMOS transistor
DE2642615C2 (de) * 1976-09-22 1986-04-24 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher
US4084175A (en) * 1976-09-30 1978-04-11 Research Corporation Double implanted planar mos device with v-groove and process of manufacture thereof
US4044452A (en) * 1976-10-06 1977-08-30 International Business Machines Corporation Process for making field effect and bipolar transistors on the same semiconductor chip
US4145703A (en) * 1977-04-15 1979-03-20 Supertex, Inc. High power MOS device and fabrication method therefor
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4116720A (en) * 1977-12-27 1978-09-26 Burroughs Corporation Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance
CA1118892A (en) * 1977-12-27 1982-02-23 John R. Edwards Semiconductor device utilizing memory cells with sidewall charge storage regions

Also Published As

Publication number Publication date
EP0018501B1 (de) 1983-05-25
IT1149830B (it) 1986-12-10
JPS55148438A (en) 1980-11-19
EP0018501A1 (de) 1980-11-12
US4252579A (en) 1981-02-24
CA1133136A (en) 1982-10-05
JPS5840343B2 (ja) 1983-09-05
DE3063421D1 (en) 1983-07-07

Similar Documents

Publication Publication Date Title
IT8021316A0 (it) Memoria mosfet ad accesso casuale ad alta densita'.
IT8319986A0 (it) Memoria ad accesso casuale mosdinamica.
FR2381354B1 (fr) Capacite perfectionnee d'ecriture en anti-memoire
BR8102741A (pt) Conjunto de memoria de alta densidade
IT8247685A0 (it) Dispositivo di memoria ad alta densita' non volatile elettricamente alternabile
EP0020477A4 (en) Dynamic random access memory.
DE3876415D1 (de) Dynamischer direktzugriffsspeicher.
IT7920569A0 (it) Memoria temporanea ad alta velocita' perfezionata.
DE3584694D1 (de) Dynamischer direktzugriffspeicher.
IT8019348A0 (it) Dispositivo per l'accumulazione dicalore.
GB2128403B (en) Random access memory
IT7926398A0 (it) Sbarra collettrice di alta capacita'.
JPS55146679A (en) Memory access device
IT1165399B (it) Memoria perfezionata
DE69016697D1 (de) Video-Direktzugriffsspeicher.
ES2025082B3 (es) Memoria dinamica vertical de alta densidad.
IT1226636B (it) Detergente in polvere ad alta densita'.
PL129681B1 (en) Sposob wytwarzania tulejki o wielokatnym kolnierzu i tloczniki do wytwarzania tulejki o wielokatnym kolnierzu
DE3585811D1 (de) Direktzugriffsspeicher.
DE3586064D1 (de) Dynamischer lese-schreib-direktzugriffsspeicher.
IT7822922A0 (it) Dispositivo per l'immagazzinamento di calore.
DE3072204D1 (de) Halbleiterspeicheranordnung.
IT8024455A0 (it) Unita' di caricamento e cambiamento fili.
JPS5634188A (en) Mos random access memory
IT8022606A0 (it) Struttura per l'indirizzamento implicito e l'accesso a dispositivi di memorizzazione.