IT8320438A0 - Procedimento per formare dispositivi a circuiti integrati complementari. - Google Patents

Procedimento per formare dispositivi a circuiti integrati complementari.

Info

Publication number
IT8320438A0
IT8320438A0 IT8320438A IT2043883A IT8320438A0 IT 8320438 A0 IT8320438 A0 IT 8320438A0 IT 8320438 A IT8320438 A IT 8320438A IT 2043883 A IT2043883 A IT 2043883A IT 8320438 A0 IT8320438 A0 IT 8320438A0
Authority
IT
Italy
Prior art keywords
procedure
integrated circuits
forming complementary
complementary integrated
circuits devices
Prior art date
Application number
IT8320438A
Other languages
English (en)
Other versions
IT8320438A1 (it
IT1168908B (it
Inventor
Louis Carl Parrillo
George William Reutlinger
Li Kong Wang
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT8320438A0 publication Critical patent/IT8320438A0/it
Publication of IT8320438A1 publication Critical patent/IT8320438A1/it
Application granted granted Critical
Publication of IT1168908B publication Critical patent/IT1168908B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6349—Deposition of epitaxial materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
IT20438/83A 1982-04-05 1983-04-01 Procedimento per formare dispositivi a circuiti integrati complementari IT1168908B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/365,396 US4435895A (en) 1982-04-05 1982-04-05 Process for forming complementary integrated circuit devices

Publications (3)

Publication Number Publication Date
IT8320438A0 true IT8320438A0 (it) 1983-04-01
IT8320438A1 IT8320438A1 (it) 1984-10-01
IT1168908B IT1168908B (it) 1987-05-20

Family

ID=23438743

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20438/83A IT1168908B (it) 1982-04-05 1983-04-01 Procedimento per formare dispositivi a circuiti integrati complementari

Country Status (11)

Country Link
US (1) US4435895A (it)
EP (1) EP0104233A4 (it)
JP (1) JPS59500540A (it)
KR (1) KR840004830A (it)
AU (1) AU543436B2 (it)
CA (1) CA1194612A (it)
ES (1) ES8403665A1 (it)
GB (1) GB2118364B (it)
HK (1) HK80486A (it)
IT (1) IT1168908B (it)
WO (1) WO1983003709A1 (it)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574465A (en) * 1982-04-13 1986-03-11 Texas Instruments Incorporated Differing field oxide thicknesses in dynamic memory device
JPS5955054A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体装置の製造方法
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
US4716451A (en) * 1982-12-10 1987-12-29 Rca Corporation Semiconductor device with internal gettering region
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4574467A (en) * 1983-08-31 1986-03-11 Solid State Scientific, Inc. N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel
JPS60106142A (ja) * 1983-11-15 1985-06-11 Nec Corp 半導体素子の製造方法
JPS60123055A (ja) * 1983-12-07 1985-07-01 Fujitsu Ltd 半導体装置及びその製造方法
ATE41265T1 (de) * 1984-03-21 1989-03-15 Siemens Ag Verfahren zum herstellen einer hochintegrierten mos-feld-effekttransistorschaltung.
US4516316A (en) * 1984-03-27 1985-05-14 Advanced Micro Devices, Inc. Method of making improved twin wells for CMOS devices by controlling spatial separation
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US5008729A (en) * 1984-06-18 1991-04-16 Texas Instruments Incorporated Laser programming of semiconductor devices using diode make-link structure
US4561170A (en) * 1984-07-02 1985-12-31 Texas Instruments Incorporated Method of making field-plate isolated CMOS devices
US4558508A (en) * 1984-10-15 1985-12-17 International Business Machines Corporation Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
JPS6197859A (ja) * 1984-10-18 1986-05-16 Matsushita Electronics Corp 相補型ｍｏｓ集積回路の製造方法
US4866002A (en) * 1985-11-26 1989-09-12 Fuji Photo Film Co., Ltd. Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof
JPH0770606B2 (ja) * 1985-11-29 1995-07-31 株式会社日立製作所 半導体装置
IT1188309B (it) * 1986-01-24 1988-01-07 Sgs Microelettrica Spa Procedimento per la fabbricazione di dispositivi elettronici integrati,in particolare transistori mos a canale p ad alta tensione
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4929565A (en) * 1986-03-04 1990-05-29 Motorola, Inc. High/low doping profile for twin well process
WO1987005443A1 (en) * 1986-03-04 1987-09-11 Motorola, Inc. High/low doping profile for twin well process
US4717683A (en) * 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4780424A (en) * 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
KR940003218B1 (ko) * 1988-03-24 1994-04-16 세이꼬 엡슨 가부시끼가이샤 반도체 장치 및 그 제조방법
US5206535A (en) * 1988-03-24 1993-04-27 Seiko Epson Corporation Semiconductor device structure
US5310690A (en) * 1988-10-31 1994-05-10 Texas Instruments Incorporated Method for forming integrated circuits having buried doped regions
US4839301A (en) * 1988-12-19 1989-06-13 Micron Technology, Inc. Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants
GB8907897D0 (en) * 1989-04-07 1989-05-24 Inmos Ltd Forming wells in semiconductor devices
US5091324A (en) * 1990-08-10 1992-02-25 Advanced Micro Devices, Inc. Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures
US5132241A (en) * 1991-04-15 1992-07-21 Industrial Technology Research Institute Method of manufacturing minimum counterdoping in twin well process
US5514616A (en) * 1991-08-26 1996-05-07 Lsi Logic Corporation Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures
KR950005464B1 (ko) * 1992-02-25 1995-05-24 삼성전자주식회사 반도체장치의 제조방법
EP0585601B1 (en) 1992-07-31 1999-04-28 Hughes Electronics Corporation Integrated circuit security system and method with implanted interconnections
US5358890A (en) * 1993-04-19 1994-10-25 Motorola Inc. Process for fabricating isolation regions in a semiconductor device
US5472887A (en) * 1993-11-09 1995-12-05 Texas Instruments Incorporated Method of fabricating semiconductor device having high-and low-voltage MOS transistors
US5434099A (en) * 1994-07-05 1995-07-18 United Microelectronics Corporation Method of manufacturing field isolation for complimentary type devices
KR100193102B1 (ko) * 1994-08-25 1999-06-15 무명씨 반도체 장치 및 그 제조방법
US5679598A (en) * 1994-12-30 1997-10-21 Lsi Logic Corporation Method of making a CMOS dynamic random-access memory (DRAM)
US5648290A (en) * 1994-12-30 1997-07-15 Lsi Logic Corporation Method of making a CMOS dynamic random-access memory (DRAM)
US5622882A (en) * 1994-12-30 1997-04-22 Lsi Logic Corporation Method of making a CMOS dynamic random-access memory (DRAM)
US5573963A (en) * 1995-05-03 1996-11-12 Vanguard International Semiconductor Corporation Method of forming self-aligned twin tub CMOS devices
KR100197656B1 (ko) * 1995-12-29 1999-07-01 김영환 반도체 에스.오.아이.소자의 제조방법
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US5783470A (en) * 1995-12-14 1998-07-21 Lsi Logic Corporation Method of making CMOS dynamic random-access memory structures and the like
US5792680A (en) * 1996-11-25 1998-08-11 Vanguard International Semiconductor Corporation Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US7217977B2 (en) * 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6391700B1 (en) * 2000-10-17 2002-05-21 United Microelectronics Corp. Method for forming twin-well regions of semiconductor devices
US6815816B1 (en) * 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US6348371B1 (en) 2001-03-19 2002-02-19 Taiwan Semiconductor Manufacturing Company Method of forming self-aligned twin wells
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
JP2003100862A (ja) * 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6897535B2 (en) * 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
WO2004055868A2 (en) 2002-12-13 2004-07-01 Hrl Laboratories, Llc Integrated circuit modification using well implants
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3418180A (en) 1965-06-14 1968-12-24 Ncr Co p-n junction formation by thermal oxydation
US3806371A (en) 1971-07-28 1974-04-23 Motorola Inc Method of making complementary monolithic insulated gate field effect transistors having low threshold voltage and low leakage current
US3865654A (en) 1972-11-01 1975-02-11 Ibm Complementary field effect transistor having p doped silicon gates and process for making the same
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
US3898105A (en) 1973-10-25 1975-08-05 Mostek Corp Method for making FET circuits
US3986896A (en) * 1974-02-28 1976-10-19 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing semiconductor devices
US3983620A (en) 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
JPS5286083A (en) 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
US4013484A (en) 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
JPS52131483A (en) 1976-04-28 1977-11-04 Hitachi Ltd Mis-type semiconductor device
US4104784A (en) 1976-06-21 1978-08-08 National Semiconductor Corporation Manufacturing a low voltage n-channel MOSFET device
US4135955A (en) 1977-09-21 1979-01-23 Harris Corporation Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation
US4214359A (en) 1978-12-07 1980-07-29 Bell Telephone Laboratories, Incorporated MOS Devices having buried terminal zones under local oxide regions
IT1166587B (it) 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
US4306916A (en) 1979-09-20 1981-12-22 American Microsystems, Inc. CMOS P-Well selective implant method
US4282648A (en) 1980-03-24 1981-08-11 Intel Corporation CMOS process
US4391650A (en) 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices

Also Published As

Publication number Publication date
KR840004830A (ko) 1984-10-24
EP0104233A4 (en) 1984-11-07
WO1983003709A1 (en) 1983-10-27
EP0104233A1 (en) 1984-04-04
IT8320438A1 (it) 1984-10-01
CA1194612A (en) 1985-10-01
GB2118364A (en) 1983-10-26
AU543436B2 (en) 1985-04-18
JPS59500540A (ja) 1984-03-29
ES521113A0 (es) 1984-04-01
AU1471883A (en) 1983-11-04
US4435895A (en) 1984-03-13
IT1168908B (it) 1987-05-20
HK80486A (en) 1986-10-31
ES8403665A1 (es) 1984-04-01
GB2118364B (en) 1985-11-06

Similar Documents

Publication Publication Date Title
IT8320438A0 (it) Procedimento per formare dispositivi a circuiti integrati complementari.
IT7926530A0 (it) Involucro piatto per dispositivi a circuiti integrati.
GB2075752B (en) Semiconductor integrated circuits
IT8322946A0 (it) Circuito di protezione per dispositivi a circuito integrato.
IT8321168A0 (it) Apparato per il collaudo ci circuiti integrati.
FI841297A0 (fi) Strykanordning foer att oeverdraga loepande aemnesbanor.
IT8124940A0 (it) Circuito integrato a semiconduttori.
NO823113L (no) Luftbaaren prosjektilutstyr.
IT8224690A0 (it) Procedimento di fabbricazione di circuiti stampati.
DE3382727D1 (de) Integrierte Halbleiterschaltungsanordnung.
IT8122944A0 (it) Procedimento di retro-corrisione per circuiti integrati.
GB2074788B (en) Semiconductor integrated circuit
ES517554A0 (es) Un dispositivo disyuntor perfeccionado.
FI831490L (fi) Saett att undvika haollfasthetsfoersaemring hos spaonskivor.
DE3175780D1 (en) Semiconductor integrated circuit devices
IT8422489A0 (it) Dispositivo per intercollegare circuiti stampati.
EP0117867A4 (en) SEMICONDUCTOR DEVICE.
ES519470A0 (es) Un dispositivo semiconductor.
NO841952L (no) Integrert omkretslaas for lukkeinnretninger
EP0054303A3 (en) Semiconductor integrated circuit
IT8121668A0 (it) Procedimento di fabbricazione di circuiti stampati.
ES519272A0 (es) Un dispositivo semiconductor moldeado en vidrio.
GB8312322D0 (en) Integrated circuits
IT8125385A0 (it) Circuiti di protezione per dispositivi a circuito integrato.
IT8220145A0 (it) Dispositivi a circuiti integrati a smiconduttori.