IT971839B - Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati - Google Patents

Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati

Info

Publication number
IT971839B
IT971839B IT32876/72A IT3287672A IT971839B IT 971839 B IT971839 B IT 971839B IT 32876/72 A IT32876/72 A IT 32876/72A IT 3287672 A IT3287672 A IT 3287672A IT 971839 B IT971839 B IT 971839B
Authority
IT
Italy
Prior art keywords
isolated
manufacture
monolithic devices
tran sistors
sistors
Prior art date
Application number
IT32876/72A
Other languages
English (en)
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT971839B publication Critical patent/IT971839B/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137Collector regions of BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00Highly-doped buried regions of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00Highly-doped buried regions of integrated devices
    • H10W15/01Manufacture or treatment
IT32876/72A 1972-01-25 1972-12-14 Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati IT971839B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH105572A CH536028A (de) 1972-01-25 1972-01-25 Verfahren zur Herstellung einer monolithischen Vorrichtung mit isolierten Transistoren

Publications (1)

Publication Number Publication Date
IT971839B true IT971839B (it) 1974-05-10

Family

ID=4201392

Family Applications (1)

Application Number Title Priority Date Filing Date
IT32876/72A IT971839B (it) 1972-01-25 1972-12-14 Processo per la fabbricazione di dispositivi monolitici con tran sistori isolati

Country Status (6)

Country Link
JP (1) JPS4886490A (de)
CA (1) CA992218A (de)
CH (1) CH536028A (de)
DE (1) DE2300412A1 (de)
FR (1) FR2169069A1 (de)
IT (1) IT971839B (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2532694B2 (ja) * 1989-11-22 1996-09-11 三菱電機株式会社 半導体装置の製造方法
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate

Also Published As

Publication number Publication date
FR2169069A1 (de) 1973-09-07
CA992218A (en) 1976-06-29
JPS4886490A (de) 1973-11-15
DE2300412A1 (de) 1973-08-02
CH536028A (de) 1973-04-15

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