ITMI20031087A1 - Circuito per la interruzione temporanea di un segnale di sincronismo - Google Patents
Circuito per la interruzione temporanea di un segnale di sincronismoInfo
- Publication number
- ITMI20031087A1 ITMI20031087A1 IT001087A ITMI20031087A ITMI20031087A1 IT MI20031087 A1 ITMI20031087 A1 IT MI20031087A1 IT 001087 A IT001087 A IT 001087A IT MI20031087 A ITMI20031087 A IT MI20031087A IT MI20031087 A1 ITMI20031087 A1 IT MI20031087A1
- Authority
- IT
- Italy
- Prior art keywords
- circuit
- temporary interruption
- synchronism signal
- synchronism
- signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
- H03K3/66—Generators producing trains of pulses, i.e. finite sequences of pulses by interrupting the output of a generator
- H03K3/70—Generators producing trains of pulses, i.e. finite sequences of pulses by interrupting the output of a generator time intervals between all adjacent pulses of one train being equal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT001087A ITMI20031087A1 (it) | 2003-05-30 | 2003-05-30 | Circuito per la interruzione temporanea di un segnale di sincronismo |
| US10/857,598 US7106119B2 (en) | 2003-05-30 | 2004-05-27 | Circuit for the temporary interruption of a sync signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT001087A ITMI20031087A1 (it) | 2003-05-30 | 2003-05-30 | Circuito per la interruzione temporanea di un segnale di sincronismo |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITMI20031087A0 ITMI20031087A0 (it) | 2003-05-30 |
| ITMI20031087A1 true ITMI20031087A1 (it) | 2004-11-30 |
Family
ID=30131111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT001087A ITMI20031087A1 (it) | 2003-05-30 | 2003-05-30 | Circuito per la interruzione temporanea di un segnale di sincronismo |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7106119B2 (it) |
| IT (1) | ITMI20031087A1 (it) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2139113A1 (en) * | 2008-06-23 | 2009-12-30 | Dialog Semiconductor GmbH | Glitch-free clock suspend and resume circuit |
| DE102008060663A1 (de) * | 2008-12-08 | 2010-06-10 | KROHNE Meßtechnik GmbH & Co. KG | Schaltungsanordnung zur Erzeugung kurzer elektrischer Impulse |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4544963A (en) * | 1984-01-16 | 1985-10-01 | Sperry Corporation | Read signal detection in ternary 3PM magnetic recording |
| KR940004499B1 (ko) * | 1991-12-23 | 1994-05-25 | 금성일렉트론 주식회사 | 브이 씨 알의 종단 기록 및 검출 회로 |
| US5623223A (en) * | 1994-10-12 | 1997-04-22 | National Semiconductor Corporation | Glitchless clock switching circuit |
| US5668982A (en) * | 1995-11-30 | 1997-09-16 | National Semiconductor Corporation | System and method for using a half-clock module to implement computer timing control circuitry |
| US5900757A (en) * | 1996-05-01 | 1999-05-04 | Sun Microsystems, Inc. | Clock stopping schemes for data buffer |
| US5789953A (en) * | 1996-05-29 | 1998-08-04 | Integrated Device Technology, Inc. | Clock signal generator providing non-integer frequency multiplication |
| JPH10154021A (ja) * | 1996-09-30 | 1998-06-09 | Toshiba Corp | クロック切換装置およびクロック切換方法 |
| US6055619A (en) * | 1997-02-07 | 2000-04-25 | Cirrus Logic, Inc. | Circuits, system, and methods for processing multiple data streams |
| US20020186787A1 (en) * | 2001-05-19 | 2002-12-12 | Fischer Michael Andrew | Binary waveform divider |
-
2003
- 2003-05-30 IT IT001087A patent/ITMI20031087A1/it unknown
-
2004
- 2004-05-27 US US10/857,598 patent/US7106119B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7106119B2 (en) | 2006-09-12 |
| ITMI20031087A0 (it) | 2003-05-30 |
| US20050017779A1 (en) | 2005-01-27 |
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