ITMI951994A0 - Procedimento e dispositivo per fabbricare un circuito integrato a semiconduttori - Google Patents

Procedimento e dispositivo per fabbricare un circuito integrato a semiconduttori

Info

Publication number
ITMI951994A0
ITMI951994A0 ITMI951994A ITMI951994A ITMI951994A0 IT MI951994 A0 ITMI951994 A0 IT MI951994A0 IT MI951994 A ITMI951994 A IT MI951994A IT MI951994 A ITMI951994 A IT MI951994A IT MI951994 A0 ITMI951994 A0 IT MI951994A0
Authority
IT
Italy
Prior art keywords
manufactureing
procedure
integrated circuit
semiconductor integrated
semiconductor
Prior art date
Application number
ITMI951994A
Other languages
English (en)
Inventor
Shigeru Harada
Original Assignee
Shigeru Harada
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17908174&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ITMI951994(A0) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Shigeru Harada filed Critical Shigeru Harada
Publication of ITMI951994A0 publication Critical patent/ITMI951994A0/it
Publication of ITMI951994A1 publication Critical patent/ITMI951994A1/it
Application granted granted Critical
Publication of IT1277670B1 publication Critical patent/IT1277670B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces
IT95MI001994A 1994-12-06 1995-09-29 Procedimento e dispositivo per fabbricare un circuito integrato a semiconduttori IT1277670B1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6302377A JPH08162425A (ja) 1994-12-06 1994-12-06 半導体集積回路装置の製造方法および製造装置

Publications (3)

Publication Number Publication Date
ITMI951994A0 true ITMI951994A0 (it) 1995-09-29
ITMI951994A1 ITMI951994A1 (it) 1997-03-29
IT1277670B1 IT1277670B1 (it) 1997-11-11

Family

ID=17908174

Family Applications (1)

Application Number Title Priority Date Filing Date
IT95MI001994A IT1277670B1 (it) 1994-12-06 1995-09-29 Procedimento e dispositivo per fabbricare un circuito integrato a semiconduttori

Country Status (6)

Country Link
US (2) US6178972B1 (it)
JP (1) JPH08162425A (it)
KR (1) KR0180283B1 (it)
DE (1) DE19521389C2 (it)
IT (1) IT1277670B1 (it)
TW (1) TW410406B (it)

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US6039059A (en) 1996-09-30 2000-03-21 Verteq, Inc. Wafer cleaning system
US6296714B1 (en) * 1997-01-16 2001-10-02 Mitsubishi Materials Silicon Corporation Washing solution of semiconductor substrate and washing method using the same
US20020157686A1 (en) * 1997-05-09 2002-10-31 Semitool, Inc. Process and apparatus for treating a workpiece such as a semiconductor wafer
JPH11200050A (ja) 1998-01-14 1999-07-27 Mitsubishi Electric Corp タングステンシリサイド膜の形成方法、半導体装置の製造方法、及び半導体ウェーハ処理装置
US6664196B1 (en) 1999-03-15 2003-12-16 Matsushita Electric Industrial Co., Ltd. Method of cleaning electronic device and method of fabricating the same
US20020031914A1 (en) * 1999-06-18 2002-03-14 Julia S. Svirchevski Post-plasma processing wafer cleaning method and system
US6429144B1 (en) * 1999-12-28 2002-08-06 Koninklijke Philips Electronics N.V. Integrated circuit manufacture method with aqueous hydrogen fluoride and nitric acid oxide etch
US6951221B2 (en) 2000-09-22 2005-10-04 Dainippon Screen Mfg. Co., Ltd. Substrate processing apparatus
US7479205B2 (en) 2000-09-22 2009-01-20 Dainippon Screen Mfg. Co., Ltd. Substrate processing apparatus
JP2002170792A (ja) * 2000-11-29 2002-06-14 Mitsubishi Electric Corp 研磨液供給装置及び研磨液供給方法、研磨装置及び研磨方法、並びに、半導体装置の製造方法
US6635565B2 (en) * 2001-02-20 2003-10-21 United Microelectronics Corp. Method of cleaning a dual damascene structure
JP4609616B2 (ja) * 2001-06-18 2011-01-12 三菱瓦斯化学株式会社 半導体装置用洗浄剤
US20030032961A1 (en) 2001-07-16 2003-02-13 Pelo Mark Joseph Devices from naturally occurring biologically derived materials
JP4101609B2 (ja) * 2001-12-07 2008-06-18 大日本スクリーン製造株式会社 基板処理方法
JP2003340386A (ja) * 2002-05-23 2003-12-02 Toshiba Corp 超音波洗浄装置及び超音波洗浄方法
US6927159B2 (en) * 2003-05-27 2005-08-09 Texas Instruments Incorporated Methods for providing improved layer adhesion in a semiconductor device
KR100734669B1 (ko) * 2003-08-08 2007-07-02 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법 및 그 장치
JP2005183407A (ja) * 2003-11-26 2005-07-07 Seiko Instruments Inc 半導体装置とその製造方法
US20060008746A1 (en) * 2004-07-07 2006-01-12 Yasunobu Onishi Method for manufacturing semiconductor device
TWI352628B (en) * 2006-07-21 2011-11-21 Akrion Technologies Inc Nozzle for use in the megasonic cleaning of substr
KR20100077859A (ko) * 2008-12-29 2010-07-08 주식회사 동부하이텍 경화 폴리머 레지듀 제거 방법
JP5787251B2 (ja) * 2011-02-28 2015-09-30 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
TWI671436B (zh) * 2017-03-17 2019-09-11 Toshiba Memory Corporation 基板處理裝置及基板處理方法

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Also Published As

Publication number Publication date
IT1277670B1 (it) 1997-11-11
TW410406B (en) 2000-11-01
KR0180283B1 (ko) 1999-04-15
JPH08162425A (ja) 1996-06-21
DE19521389A1 (de) 1996-06-13
US6178972B1 (en) 2001-01-30
ITMI951994A1 (it) 1997-03-29
US20010000199A1 (en) 2001-04-12
DE19521389C2 (de) 2001-06-07
US6283835B1 (en) 2001-09-04
KR960026642A (ko) 1996-07-22

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