ITRM920707A1 - Apparecchio e metodo per la protezione di memorie da scritture spurie. - Google Patents
Apparecchio e metodo per la protezione di memorie da scritture spurie.Info
- Publication number
- ITRM920707A1 ITRM920707A1 IT000707A ITRM920707A ITRM920707A1 IT RM920707 A1 ITRM920707 A1 IT RM920707A1 IT 000707 A IT000707 A IT 000707A IT RM920707 A ITRM920707 A IT RM920707A IT RM920707 A1 ITRM920707 A1 IT RM920707A1
- Authority
- IT
- Italy
- Prior art keywords
- signal
- generation
- memory device
- data
- spury
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Mobile Radio Communication Systems (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US76989691A | 1991-10-01 | 1991-10-01 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITRM920707A0 ITRM920707A0 (it) | 1992-09-28 |
| ITRM920707A1 true ITRM920707A1 (it) | 1994-03-28 |
| IT1258856B IT1258856B (it) | 1996-03-01 |
Family
ID=25086828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITRM920707A IT1258856B (it) | 1991-10-01 | 1992-09-28 | Apparecchio e metodo per la protezione di memorie da scritture spurie. |
Country Status (5)
| Country | Link |
|---|---|
| CA (1) | CA2097308A1 (it) |
| FR (1) | FR2681965A1 (it) |
| IT (1) | IT1258856B (it) |
| MX (1) | MX9205634A (it) |
| WO (1) | WO1993007565A1 (it) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6026293A (en) * | 1996-09-05 | 2000-02-15 | Ericsson Inc. | System for preventing electronic memory tampering |
| GB2356952B (en) * | 1996-12-25 | 2001-07-25 | Fujitsu Ltd | Semiconductor memory device |
| JP4154006B2 (ja) * | 1996-12-25 | 2008-09-24 | 富士通株式会社 | 半導体記憶装置 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4245344A (en) * | 1979-04-02 | 1981-01-13 | Rockwell International Corporation | Processing system with dual buses |
| US4493031A (en) * | 1982-08-25 | 1985-01-08 | At&T Bell Laboratories | Memory write protection using timers |
| JPS6124091A (ja) * | 1984-07-12 | 1986-02-01 | Nec Corp | メモリ回路 |
| US4742469A (en) * | 1985-10-31 | 1988-05-03 | F.M.E. Corporation | Electronic meter circuitry |
| US4816654A (en) * | 1986-05-16 | 1989-03-28 | American Telephone And Telegraph Company | Improved security system for a portable data carrier |
| US4843385A (en) * | 1986-07-02 | 1989-06-27 | Motorola, Inc. | Electronic lock system for a two-way radio |
| FR2608803B1 (fr) * | 1986-12-19 | 1991-10-25 | Eurotechnique Sa | Dispositif de protection d'une memoire morte effacable et reprogrammable |
| US5001670A (en) * | 1987-02-06 | 1991-03-19 | Tektronix, Inc. | Nonvolatile memory protection |
| JPS63271679A (ja) * | 1987-04-30 | 1988-11-09 | Toshiba Corp | デ−タ書込み方式 |
| US4860341A (en) * | 1987-06-02 | 1989-08-22 | Motorola, Inc. | Radiotelephone credit card call approval synchronization |
| US4970692A (en) * | 1987-09-01 | 1990-11-13 | Waferscale Integration, Inc. | Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin |
| JPH0648838B2 (ja) * | 1988-07-18 | 1994-06-22 | 株式会社田村電機製作所 | 公衆電話機 |
| FI86922C (fi) * | 1990-01-05 | 1992-10-26 | Raha Automaattiyhdistys | Foerfarande och anordning foer kontrollering av inskrivning i ett minne |
-
1992
- 1992-08-03 WO PCT/US1992/006455 patent/WO1993007565A1/en not_active Ceased
- 1992-08-03 CA CA002097308A patent/CA2097308A1/en not_active Abandoned
- 1992-09-28 IT ITRM920707A patent/IT1258856B/it active IP Right Grant
- 1992-10-01 FR FR9211978A patent/FR2681965A1/fr active Pending
- 1992-10-01 MX MX9205634A patent/MX9205634A/es unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CA2097308A1 (en) | 1993-04-02 |
| ITRM920707A0 (it) | 1992-09-28 |
| WO1993007565A1 (en) | 1993-04-15 |
| FR2681965A1 (fr) | 1993-04-02 |
| MX9205634A (es) | 1993-04-01 |
| IT1258856B (it) | 1996-03-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted |