ITTO20040470A1 - Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica. - Google Patents

Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.

Info

Publication number
ITTO20040470A1
ITTO20040470A1 IT000470A ITTO20040470A ITTO20040470A1 IT TO20040470 A1 ITTO20040470 A1 IT TO20040470A1 IT 000470 A IT000470 A IT 000470A IT TO20040470 A ITTO20040470 A IT TO20040470A IT TO20040470 A1 ITTO20040470 A1 IT TO20040470A1
Authority
IT
Italy
Prior art keywords
reading
verification
memory cells
ramp
level memory
Prior art date
Application number
IT000470A
Other languages
English (en)
Inventor
Luigi Pascucci
Paolo Rolandi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000470A priority Critical patent/ITTO20040470A1/it
Publication of ITTO20040470A1 publication Critical patent/ITTO20040470A1/it
Priority to US11/178,240 priority patent/US7397702B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
IT000470A 2004-07-08 2004-07-08 Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica. ITTO20040470A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000470A ITTO20040470A1 (it) 2004-07-08 2004-07-08 Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.
US11/178,240 US7397702B2 (en) 2004-07-08 2005-07-08 Read/verify circuit for multilevel memory cells with ramp read voltage, and read/verify method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000470A ITTO20040470A1 (it) 2004-07-08 2004-07-08 Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.

Publications (1)

Publication Number Publication Date
ITTO20040470A1 true ITTO20040470A1 (it) 2004-10-08

Family

ID=35757205

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000470A ITTO20040470A1 (it) 2004-07-08 2004-07-08 Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.

Country Status (2)

Country Link
US (1) US7397702B2 (it)
IT (1) ITTO20040470A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8045381B2 (en) * 2005-05-09 2011-10-25 Stmicroelectronics Sa Device for protecting a memory against attacks by error injection
US7800951B2 (en) * 2007-08-20 2010-09-21 Marvell World Trade Ltd. Threshold voltage digitizer for array of programmable threshold transistors
US7948802B2 (en) 2007-12-04 2011-05-24 Micron Technology, Inc. Sensing memory cells
US7830708B1 (en) * 2009-04-22 2010-11-09 Seagate Technology Llc Compensating for variations in memory cell programmed state distributions
US8363478B1 (en) * 2010-02-17 2013-01-29 Marvell International Ltd. Group based read reference voltage management in flash memory
US8238158B2 (en) * 2010-08-04 2012-08-07 Texas Instruments Incorporated Programming of memory cells in a nonvolatile memory using an active transition control
TWI600009B (zh) 2016-11-04 2017-09-21 財團法人工業技術研究院 可變電阻記憶體電路以及可變電阻記憶體電路之寫入方法
US10354728B2 (en) 2017-06-28 2019-07-16 Sandisk Technologies Llc Write verification and resistive state determination based on cell turn-on characteristics for resistive random access memory
US10256402B1 (en) 2017-09-25 2019-04-09 Sandisk Technologies Llc ReRAM read state verification based on cell turn-on characteristics
TWI670491B (zh) 2018-12-10 2019-09-01 財團法人工業技術研究院 電化學製程裝置以及電化學製程裝置的操作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508958A (en) * 1994-09-29 1996-04-16 Intel Corporation Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage
US5694356A (en) * 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5856946A (en) * 1997-04-09 1999-01-05 Advanced Micro Devices, Inc. Memory cell programming with controlled current injection
IT1293644B1 (it) * 1997-07-25 1999-03-08 Sgs Thomson Microelectronics Circuito e metodo di lettura di celle di una matrice di memoria analogica, in particolare di tipo flash
EP0908895A1 (en) * 1997-10-09 1999-04-14 STMicroelectronics S.r.l. Controlled hot-electron writing method for non-volatile memory cells
IT1303204B1 (it) * 1998-11-27 2000-10-30 St Microelectronics Srl Metodo di programmazione di celle di memoria non volatile ad elevataprecisione, con velocita' di programmazione ottimizzata.
US6275417B1 (en) * 1999-10-08 2001-08-14 Aplus Flash Technology, Inc. Multiple level flash memory
US6275415B1 (en) * 1999-10-12 2001-08-14 Advanced Micro Devices, Inc. Multiple byte channel hot electron programming using ramped gate and source bias voltage
US6515902B1 (en) * 2001-06-04 2003-02-04 Advanced Micro Devices, Inc. Method and apparatus for boosting bitlines for low VCC read
US6646495B2 (en) * 2001-12-31 2003-11-11 Texas Instruments Incorporated Threshold voltage adjustment scheme for increased output swing
EP1646051B1 (en) * 2004-10-08 2008-03-05 STMicroelectronics S.r.l. Memory device and method for operating the same with high rejection of the noise on the high-voltage supply line
EP1686591B1 (en) * 2005-01-28 2008-01-09 STMicroelectronics S.r.l. A memory device with a ramp-like voltage biasing structure based on a current generator
DE602005018738D1 (de) * 2005-03-03 2010-02-25 St Microelectronics Srl Speichervorrichtung mit auf Zeitverschiebung basierender Referenzzellenemulation
ITVA20050028A1 (it) * 2005-05-03 2006-11-04 St Microelectronics Srl Generatore di rampa e relativa decodifica di riga per memoria flash

Also Published As

Publication number Publication date
US7397702B2 (en) 2008-07-08
US20060028872A1 (en) 2006-02-09

Similar Documents

Publication Publication Date Title
DE602005004831D1 (de) Magnetische Multibit-Speicherzellenvorrichtung mit wahlfreiem Zugriff
EP1929482A4 (en) PORTABLE DATA STORAGE USING SLC AND MLC FLASH MEMORY
ATE510287T1 (de) Kopplungskompensation bei nichtflüchtiger speicherung
ITTO20040470A1 (it) Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.
DE602005012028D1 (de) Nichtflüchtige Halbleiterspeicheranordnung und Leseverfahren
TWI367487B (en) Flash memory programming and verification method with reduced leakage current
DE602007011736D1 (de) Leseoperation für nichtflüchtige speicherung mit floating-gate-kopplungskompensation
TWI348757B (en) Nonvolatile rewriteable memory cell comprising a resistivity-switching oxide or nitride and an antifuse
DE60303835D1 (de) Magnetischer Direktzugriffsspeicher sowie entsprechendes Leseverfahren
WO2008057822A3 (en) Nonvolatile memory with variable read threshold
TWI370459B (en) Method and system for adaptively finding reference voltages for reading data from a mlc flash memory
GB0520105D0 (en) System and method of reading non-volatile computer memory
WO2008083196A3 (en) Margined neighbor reading for non-volatile memory read operations including coupling compensation
WO2007098044A3 (en) Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
WO2008008466A3 (en) Current sensing for flash
DE60303721D1 (de) Speichervorrichtung mit Speicherzelleinheiten aus einer Speicherzelle und einer komplementären Speicherzelle, und ein Leseverfahren
EP1721321A4 (en) REMANENT MEMORY ASSEMBLY HAVING SIMULTANEOUS WRITE AND ERASE CHARACTERISTICS
WO2007143398A3 (en) Verify operation for non-volatile storage using different voltages
DE602005001829D1 (de) Magnetische Multibit-Direktzugriffspeicheranordnung und deren Schreibverfahren
WO2007078885A3 (en) Multi-level memory cell sensing
TWI318406B (en) Systems and method for alternate row-based reading and writing for non-volatile memory
TW200710861A (en) Improved read mode for flash memory
ITTO20021035A1 (it) Dispositivo di memoria non volatile a lettura e scrittura simulante.
ITRM20020493A0 (it) Memoria cam non volatile di tipo and.
TW200721175A (en) Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage