ITTO20120675A1 - Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione - Google Patents

Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione

Info

Publication number
ITTO20120675A1
ITTO20120675A1 IT000675A ITTO20120675A ITTO20120675A1 IT TO20120675 A1 ITTO20120675 A1 IT TO20120675A1 IT 000675 A IT000675 A IT 000675A IT TO20120675 A ITTO20120675 A IT TO20120675A IT TO20120675 A1 ITTO20120675 A1 IT TO20120675A1
Authority
IT
Italy
Prior art keywords
emptying
enrichment
manufacturing
phemt device
phemt
Prior art date
Application number
IT000675A
Other languages
English (en)
Inventor
Alessandro Chini
Claudio Lanzieri
Original Assignee
Selex Sistemi Integrati Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Selex Sistemi Integrati Spa filed Critical Selex Sistemi Integrati Spa
Priority to IT000675A priority Critical patent/ITTO20120675A1/it
Publication of ITTO20120675A1 publication Critical patent/ITTO20120675A1/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/05Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/84Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/86Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of Schottky-barrier gate FETs
IT000675A 2011-08-01 2012-07-30 Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione ITTO20120675A1 (it)

Priority Applications (1)

Application Number Priority Date Filing Date Title
IT000675A ITTO20120675A1 (it) 2011-08-01 2012-07-30 Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITTO20110713 2011-08-01
IT000675A ITTO20120675A1 (it) 2011-08-01 2012-07-30 Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione

Publications (1)

Publication Number Publication Date
ITTO20120675A1 true ITTO20120675A1 (it) 2013-02-02

Family

ID=44653489

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000675A ITTO20120675A1 (it) 2011-08-01 2012-07-30 Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione

Country Status (4)

Country Link
US (1) US8610173B2 (it)
EP (1) EP2555242B1 (it)
ES (1) ES2518917T3 (it)
IT (1) ITTO20120675A1 (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
US9773877B2 (en) 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US11791385B2 (en) 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
EP2040299A1 (en) * 2007-09-12 2009-03-25 Forschungsverbund Berlin e.V. Electrical devices having improved transfer characteristics and method for tailoring the transfer characteristics of such an electrical device
US9847411B2 (en) * 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9755059B2 (en) 2013-06-09 2017-09-05 Cree, Inc. Cascode structures with GaN cap layers
US9502535B2 (en) * 2015-04-10 2016-11-22 Cambridge Electronics, Inc. Semiconductor structure and etch technique for monolithic integration of III-N transistors
US10720428B2 (en) * 2015-11-10 2020-07-21 Qorvo Us, Inc. High bandgap Schottky contact layer device
US10811407B2 (en) * 2019-02-04 2020-10-20 Win Semiconductor Corp. Monolithic integration of enhancement mode and depletion mode field effect transistors
US11177379B2 (en) * 2019-06-19 2021-11-16 Win Semiconductors Corp. Gate-sinking pHEMTs having extremely uniform pinch-off/threshold voltage
US11081485B2 (en) * 2019-10-23 2021-08-03 Win Semiconductors Corp. Monolithic integrated circuit device having gate-sinking pHEMTs

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2551427B2 (ja) 1987-03-12 1996-11-06 富士通株式会社 半導体装置及びその製造方法
JPH02148740A (ja) 1988-11-29 1990-06-07 Fujitsu Ltd 半導体装置及びその製造方法
KR100379619B1 (ko) 2000-10-13 2003-04-10 광주과학기술원 단일집적 e/d 모드 hemt 및 그 제조방법
US6703638B2 (en) 2001-05-21 2004-03-09 Tyco Electronics Corporation Enhancement and depletion-mode phemt device having two ingap etch-stop layers
US7449728B2 (en) 2003-11-24 2008-11-11 Tri Quint Semiconductor, Inc. Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
US7183592B2 (en) 2004-05-26 2007-02-27 Raytheon Company Field effect transistor
US20060175631A1 (en) 2005-02-04 2006-08-10 Raytheon Company Monolithic integrated circuit having enhanced breakdown voltage
US7321132B2 (en) 2005-03-15 2008-01-22 Lockheed Martin Corporation Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same
JP5431652B2 (ja) * 2007-04-02 2014-03-05 ルネサスエレクトロニクス株式会社 半導体装置
JP2008263146A (ja) 2007-04-13 2008-10-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2009032729A (ja) 2007-07-24 2009-02-12 Sony Corp スイッチ素子および電子機器
JP2010016089A (ja) 2008-07-02 2010-01-21 Nec Electronics Corp 電界効果トランジスタ、その製造方法、及び半導体装置
US8390000B2 (en) 2009-08-28 2013-03-05 Transphorm Inc. Semiconductor devices with field plates

Also Published As

Publication number Publication date
US20130062667A1 (en) 2013-03-14
EP2555242B1 (en) 2014-07-23
ES2518917T3 (es) 2014-11-05
EP2555242A1 (en) 2013-02-06
US8610173B2 (en) 2013-12-17

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