ITTO930036A0 - Circuito integrato a semiconduttore e relativo procedimento di collau-do. - Google Patents

Circuito integrato a semiconduttore e relativo procedimento di collau-do.

Info

Publication number
ITTO930036A0
ITTO930036A0 IT93TO36A ITTO930036A ITTO930036A0 IT TO930036 A0 ITTO930036 A0 IT TO930036A0 IT 93TO36 A IT93TO36 A IT 93TO36A IT TO930036 A ITTO930036 A IT TO930036A IT TO930036 A0 ITTO930036 A0 IT TO930036A0
Authority
IT
Italy
Prior art keywords
integrated circuit
semiconductor integrated
testing procedure
related testing
procedure
Prior art date
Application number
IT93TO36A
Other languages
English (en)
Inventor
Kiyotoshi Ueda
Kazuhiro Nishimura
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITTO930036A0 publication Critical patent/ITTO930036A0/it
Publication of ITTO930036A1 publication Critical patent/ITTO930036A1/it
Application granted granted Critical
Publication of IT1260860B publication Critical patent/IT1260860B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
ITTO930036A 1992-01-23 1993-01-22 Circuito integrato a semiconduttore e relativo procedimento di collaudo IT1260860B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4009860A JPH05198637A (ja) 1992-01-23 1992-01-23 半導体集積回路及びそのテスト方法

Publications (3)

Publication Number Publication Date
ITTO930036A0 true ITTO930036A0 (it) 1993-01-22
ITTO930036A1 ITTO930036A1 (it) 1994-07-22
IT1260860B IT1260860B (it) 1996-04-29

Family

ID=11731893

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO930036A IT1260860B (it) 1992-01-23 1993-01-22 Circuito integrato a semiconduttore e relativo procedimento di collaudo

Country Status (3)

Country Link
US (1) US5367263A (it)
JP (1) JPH05198637A (it)
IT (1) IT1260860B (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787096A (en) * 1996-04-23 1998-07-28 Micron Technology, Inc. Circuit and method for testing an integrated circuit
SG89232A1 (en) * 1996-05-14 2002-06-18 Texas Instr Singapore Pte Ltd A process of testing memory parts and equipment for conducting the testing
SG85066A1 (en) * 1996-05-14 2001-12-19 Texas Instr Singapore Pte Ltd Test board and process of testing wide word memoryparts
US5727001A (en) 1996-08-14 1998-03-10 Micron Technology, Inc. Circuit and method for testing an integrated circuit
US5754559A (en) * 1996-08-26 1998-05-19 Micron Technology, Inc. Method and apparatus for testing integrated circuits
TW442945B (en) * 1998-11-20 2001-06-23 Sony Computer Entertainment Inc Integrated circuit chip, integrated circuit device, printed circuit board and electronic machine
US20040051550A1 (en) * 2002-09-12 2004-03-18 Ma David Suitwai Semiconductor die isolation system
WO2005052615A1 (en) * 2003-11-19 2005-06-09 Honeywell International Inc. Pseudo random verification of a device under test in the presence of byzantine faults
JP2006106132A (ja) * 2004-09-30 2006-04-20 Sharp Corp 表示駆動回路および表示装置
US7475318B2 (en) * 2005-01-28 2009-01-06 Honeywell International Inc. Method for testing the sensitive input range of Byzantine filters
FR3035750B1 (fr) * 2015-04-30 2018-06-15 Schneider Electric Industries Sas Dispositif de protection d'un reseau electrique
KR102388044B1 (ko) * 2015-10-19 2022-04-19 삼성전자주식회사 테스트 장치 및 이를 포함하는 테스트 시스템

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
US4956602A (en) * 1989-02-14 1990-09-11 Amber Engineering, Inc. Wafer scale testing of redundant integrated circuit dies
US5059899A (en) * 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making

Also Published As

Publication number Publication date
ITTO930036A1 (it) 1994-07-22
IT1260860B (it) 1996-04-29
JPH05198637A (ja) 1993-08-06
US5367263A (en) 1994-11-22

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Legal Events

Date Code Title Description
0001 Granted