JP2000311902A - Compound semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a good base ohmic contact by a method wherein an edge thinning layer which contains an InGaP layer is installed between a base electrode and a base layer, and a region which contains Pt or Pd in a specific amount is provided between the base electrode and a collector layer. SOLUTION: A base electrode 504 is formed on a collector layer 501, a base layer 502 and an edge thinning layer 503 which conains an InGaP layer. A Pt or Pd and semiconductor alloying region 505 which reaches the edge thinning layer 503 containing the InGaP layer and the base layer 502 is installed from the lower part of the base electrode 504. The amount of Pt or Pd which is contained in the alloying region 505 is set at 10.75 to 32.25 μg/cm2 or 6.00 to 18.00 μg/cm2 per unit area. As a result, it is possible to form this compound semiconductor device in which a good base ohmic contact is obtained, which is thermally stable and whose reliability is high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compound semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a base electrode of a vertical heterojunction bipolar transistor (HBT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventional AlGaAs / GaAs HBTs use p-type GaAs.
Base layer is n-type AlGaAs emitter layer (edge thinning layer)
The base electrode is formed on this edge thinning layer by covering with a thin layer, and heat treatment is performed to alloy the base electrode with the emitter layer, thereby making ohmic contact with the base layer via the edge thinning layer. ing. According to this structure, surface recombination of the base layer can be suppressed, and the characteristics and reliability of the element can be improved. At this time, Pt, Pd, or the like is often used for the base electrode. In particular, Pt undergoes a significant alloying reaction with AlGaAs and GaAs at 350 ° C. or higher, and the penetration depth of Pt is about the thickness of Pt. It is known to double. This can be seen in Tokuhei 7-8
No. 9556 and the like. Therefore, the thickness of Pt is generally equal to or more than half the thickness of the thinned AlGaAs edge thinning layer.

In recent years, InGaP / GaAs HBTs can be improved in high frequency characteristics due to the characteristics of InGaP materials as compared with AlGaAs / GaAs HBTs.
Similar to the structure of the AlGaAs / GaAs HBT, a structure was developed in which an n-type InGaP edge thinning layer was left on a p-type GaAs base layer, a base electrode was formed on the edge thinning layer, and ohmic contact was made via the edge thinning layer. This is disclosed in JP-A-7-106343. This structure will be described with reference to FIG.

An n ⁺ -type GaAs collector contact layer 902 and an i-type GaAs collector layer 90 are formed on a semi-insulating GaAs substrate 901.
4. p-type GaAs base layer 905, n-type InGaP emitter layer 9
06, n-type AlGaAs emitter protective layer 908, n-type GaAs emitter layer 909, n ⁺ -type InGaAs emitter cap layer 910
Are stacked in this order. Collector contact layer 9
02, InGaP emitter layer 906, emitter cap layer 9
A collector electrode 913, a base electrode 911, and an emitter electrode 912 are formed on the respective layers 10. Below the base electrode 911, an alloyed region 921 reaching the base layer 905 is formed. A sidewall 920 is formed on the side wall of the emitter mesa.

A method of manufacturing the base electrode 911 is to form a multi-layer metal having a lowermost layer of Pd or Pt on the InGaP emitter layer 906 and form an alloyed region 921 reaching the base layer 905 by heat treatment at 350 ° C. for 15 minutes. I do. Thereby, an ohmic contact is made with the base layer 905. The thickness of Pd or Pt used for the base electrode 911 is about 20 nm, n-type
The thickness of the InGaP emitter layer 906 is about 30 nm,
Same as for aAs.

[0006]

However, when the semiconductor device is manufactured by the method described in Japanese Patent Application Laid-Open No. 7-106343, there is a problem that the characteristics of the semiconductor element are liable to be deteriorated. According to the results of intensive studies conducted by the inventor on the cause, it has been found that a problem that the element characteristics are likely to be degraded by a high-temperature heat treatment or a long-time heat treatment even at a low temperature during the formation of the base electrode. Was. Therefore, good characteristics can be obtained when forming a collector ohmic electrode having an AuGe / Ni / Au structure.
℃ heat treatment at the same time as the heat treatment when forming the base electrode,
Alternatively, it could not be performed after the formation of the base electrode or for a long time (at 330 ° C. for one hour) to form a polyimide film (interlayer insulating film) on the substrate after the device was manufactured. In addition, it has been newly found that a device having a structure in which the side wall of the emitter mesa is close to the base electrode is liable to cause a problem of causing a leak current between the emitter and the base.

[0007]

The invention according to claim 1 is
In a heterojunction bipolar transistor having a vertical structure in which at least a collector contact layer, a collector layer, a base layer, and an emitter layer are sequentially stacked on a compound semiconductor substrate, InGaP is provided between a base electrode and the base layer. And an edge thinning layer including a layer, and between the base electrode and the collector layer,
0.75 to 32.25 μg / cm ² Pt or 6.00
It has a structure characterized by having a region containing Pd of １８18.00 μg / cm ² .

The semiconductor device according to the present invention will be described with reference to FIG. FIG. 3 is a schematic view near the base electrode. A base electrode 504 is formed on the collector layer 501, the base layer 502, and the edge thinning layer 503 including the InGaP layer.
There is an edge thinning layer 503 including an InGaP layer from under the base electrode 504 and an alloyed region 505 of Pt or Pd and a semiconductor reaching the base layer 502. The amount of Pt or Pd contained in the alloy region 505 is 1 per unit area.
0.75 to 32.25 μg / cm ² , or 6.00 to
18.00 μg / cm ² . In addition, when the alloy region reaches the collector layer, the device characteristics deteriorate, and the alloy region does not reach the collector layer.

The amount of Pt or Pd per unit area is the amount of Pt or Pd in the lowermost layer of the electrode completely diffusing and reacting with the semiconductor layer and not reacting with the semiconductor layer.
Does not include more than layer. For example, the base electrode is Pt / Ti /
Although a four-layer structure of Pt / Au is often used, the lowermost layer of Pt reacts with the semiconductor layer, but the second layer of Ti acts as a barrier layer to prevent interdiffusion between the upper and lower layers. Therefore 3
Pt in the layer does not react with the semiconductor layer and is not included in the range. The amount of Pt or Pd is 10.75 and 6.00 μg, respectively.
If it is less than / cm ² , contact with the base layer cannot be made, and the amounts of Pt and Pd are 32.25 and 18.00, respectively.
When the amount is more than μg / cm ^{2, the} reaction is further promoted by heat treatment or the like, and the characteristic tends to be deteriorated.

[0010] The optimum amount is described in the prior art.
The amount of Pt or Pd is much smaller than that of AlGaAs. According to the results of our experiments, the reaction between the InGaP layer and Pt and Pd proceeds at a lower temperature (300 ° C or lower) than in the case of the AlGaAs layer.
It is considered that the reaction is much easier when the InGaP edge thinning layer is used than when the AlGaAs edge thinning layer is used. Therefore, if the optimum amount of Pt or Pd, which has been examined in detail in the case of AlGaAs, is applied directly to the case of InGaP, the reaction proceeds too much, and it is considered that the diffusion to the collector layer causes deterioration of the characteristics of the device. In order to obtain good contact, the amount of Pt or Pd should be 15.05 to 2 respectively.
7.95 μg / cm ² , 8.40 to 15.60 μg / cm ²
It is preferred that The thickness of the base layer is preferably from 50 nm to 100 nm, at which high high-frequency characteristics can be obtained.

The edge thinning layer containing InGaP may be a single layer of InGaP, or an AlGaAs layer, GaAs, in addition to an InGaP layer.
It may be a multilayer including layers. AlGaAs when an AlGaAs layer, GaAs layer, etc. are included between the InGaP layer and the base electrode
It is desirable that the thickness of the layer, the GaAs layer, and the like be 5 nm or less.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the edge thinning layer between the base electrode and the base layer has a thickness of 20 to 40 nm.

When the layer thickness is less than 20 nm, recombination of electrons and holes easily occurs on the surface of the base layer, and the current gain is reduced. On the other hand, if the thickness is 40 nm or more, the edge thinning layer is not completely depleted, which may cause a problem that a leak current flows from the base electrode to the emitter.

According to a third aspect of the present invention, the emitter layer has a mesa shape, and the distance between the emitter mesa side wall and the base electrode is 150 to 350 nm. Become.

If the distance between the emitter mesa side wall and the base electrode is reduced to improve the high-frequency characteristics by reducing the base resistance, there is a possibility that a leak current may occur between the emitter and the base. This is because Pt or Pd diffuses not only in the depth direction but also in the lateral direction, that is, in the direction of the emitter mesa side wall. In particular, the distance between the emitter mesa side wall and the base electrode is reduced to reduce the base resistance. It is considered that in the case of the reduced element, the amount of Pt or Pd as in the conventional case was excessively diffused in the lateral direction, causing a current to flow directly from the base electrode to the emitter, resulting in deterioration of characteristics. Leakage current occurred when the distance between the emitter mesa side wall and the base electrode was less than 150 nm. If it is larger than 350 nm, high frequency characteristics cannot be expected. However, according to the configuration of the present invention, high-frequency characteristics can be improved without generating a leak current between the emitter and the base.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a heterojunction bipolar transistor having a vertical structure in which at least a collector contact layer, a collector layer, a base layer, and an emitter layer are sequentially stacked on a compound semiconductor substrate. In the region where the base electrode is formed, by etching while leaving a part of the emitter layer, an edge thinning layer including at least an InGaP layer is formed, and Pt or Pd having a thickness of 5 to 15 nm is formed on the edge thinning layer. A method for manufacturing a compound semiconductor device, characterized in that Pt or Pd is diffused from an edge thinning layer to a base layer by vapor deposition and heat treatment.

The Pt or Pd having a thickness of 5 to 15 nm is Pt or 6.00 to 32.25 μg / cm ² of claim 1.
P18.0 μg / cm ² . If the amount is less than this range, contact with the base layer cannot be obtained, and if the amount is too large, the reaction proceeds excessively due to heat treatment or the like and reaches the collector layer, which tends to cause characteristic deterioration. The thickness of Pt or Pd is preferably 7 to 13 nm in order to lower the contact resistance. By this method, the vicinity of the base electrode becomes as shown in FIG. 3 as described above.

According to a fifth aspect of the present invention, the heat treatment is performed at 420 ° C.
According to the fourth aspect of the present invention, there is provided a method for manufacturing a compound semiconductor device.

When the heat treatment temperature is 420 ° C. or more, Pt or Pd
Can be completed, but if the temperature is lower than that, it is considered that the reaction is stopped by an incomplete reaction.

In order to prevent element destruction, 550
It is desirable that the temperature is not more than ° C. This heat treatment temperature is higher than before. The heat treatment time is preferably 2 to 5 minutes.

According to a sixth aspect of the present invention, in the compound semiconductor device according to the fifth aspect of the present invention, at the time of raising the temperature for performing the heat treatment, the rate of temperature rise between 250 ° C. and 420 ° C. is 10 ° C. or more per minute. According to the manufacturing method.

If the rate of temperature rise is 10 ° C. or less per minute, it becomes difficult to make contact, and if the distance between the side wall of the emitter mesa and the base electrode is reduced, a leak current is likely to occur between the emitter and the base. This is because the reaction of Pt or Pd occurs at a lower temperature in the InGaP layer than in the GaAs layer, so that at low temperatures the lateral diffusion in the InGaP layer is greater than the vertical diffusion in the GaAs layer. It is thought that Pt required for the reaction in the vertical direction becomes insufficient, or diffusion to the side wall of the emitter mesa proceeds more. Therefore, the temperature is lower than the heat treatment temperature.
It is considered important to shorten the time at 50 ° C to 420 ° C. At 250 ° C. or lower, the InGaP layer and Pt or P
Since the reaction of d hardly occurs, it seems that any rate of temperature increase may be used.

[0023]

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIG. Semi-insulating GaAs substrate 1
N ⁺ type GaAs collector contact layer 102 (impurity concentration 5.0 × 10 ¹⁸ cm ⁻³ , film thickness 500 nm), n
-Type InGaP etching stopper layer 103 (impurity concentration 3.0 × 10 ¹⁸ cm ⁻³ , film thickness 20 nm), n-type GaAs collector layer 104 (impurity concentration 3.0 × 10 ¹⁶ cm ⁻³ , film thickness 700 nm), p ⁺ Type GaAs base layer 105 (impurity concentration 4.0 × 10 ¹⁹ cm ⁻³ , film thickness 70 nm), n-type InGaP emitter layer 106 (impurity concentration 5.0 × 10 ¹⁷ cm ⁻³ , film thickness 70 nm), n-type GaAs Emitter layer 107, n ⁺ type InGaA
The s emitter cap layer 108 is stacked in this order by MOCVD. Even if a gas source MBE or the like is used, the layers can be similarly laminated.

By photolithography, a portion serving as an emitter is masked, and the other portions are etched with a mixed solution of citric acid and hydrogen peroxide. Since this mixed solution does not etch InGaP, when the InGaP layer 106 is exposed on the surface, the etching stops there. In other than the emitter area
Etch GaP emitter layer 106 with hydrochloric acid to about 40 nm
In this case, the edge thinning layer is formed and the emitter mesa shape is formed.

Next, a portion serving as an emitter and a base is masked by photolithography, and the other portions are etched. InGaP is etched with hydrochloric acid, and GaAs is etched with a mixture of citric acid and hydrogen peroxide to expose the surface of the GaAs collector contact layer 102. Subsequently, an electrode is formed. The base electrode region is exposed by photolithography, and Pt / Ti / Pt / Au are respectively exposed to 10/50/50.
/ 60 nm deposited and lift-off for base electrode 111
To form Similarly, lift-off causes emitter electrode 1
12/100/50/50 / 50n of WN / Ti / Pt / Au
m, AuGe / Ni / Au is 100/15 on the collector electrode 113
/ 100 nm. Thereafter, a heat treatment is performed at 420 ° C. for 1 minute at a rate of temperature increase of 5 ° C./sec to form a base electrode 11
1. The collector electrode 113 makes ohmic contact with the base layer 105 and the collector contact layer 102, respectively. Thereafter, element separation is performed by etching or the like, an interlayer insulating film is formed, and wiring (not shown) is formed by plating or vapor deposition.

The emitter layer may be a single layer of InGaP or a multilayer containing GaAs, AlGaAs, etc. in addition to InGaP. The base layer may be an AlGaAs or GaAs graded layer. Table 1 summarizes the results of comparing the characteristics of HBTs manufactured by changing the thickness of Pt in the lowermost layer of the base electrode 111.

[0027]

[Table 1]

As shown in Table 1, good contact was obtained with a thickness in the range of 5 to 15 nm. Similar results were obtained by using Pd instead of Pt of the base electrode.

Next, leave between the base electrode and the base layer.
Table 2 summarizes the results of comparing the characteristics of HBTs manufactured by changing the thickness of the InGaP layer.

[0030]

[Table 2]

Heat treatment is performed at 390 ° C. for 1 minute and at 420 ° C. for 1 minute.
Further, a heat treatment at 390 ° C. for 1 minute was further added to the device performed for 1 minute, and the characteristics were examined. In the element heat-treated at 420 ° C. for 1 minute, the characteristics did not change even after the heat treatment was added. However, in the element heat-treated at 390 ° C. for 1 minute, the contact resistance was reduced by the additional heat treatment.
It was higher than the device that was heat-treated at ℃ for 1 minute. Therefore, 3
It is considered that the reaction was incomplete with the heat treatment at 90 ° C. After the heat treatment at 390 ° C. for 1 minute, the additional heat treatment at 420 ° C. for 1 minute was performed. However, the contact resistance was higher than that of the element heat-treated at 420 ° C. for 1 minute.

Further, Table 3 summarizes the results of comparing the characteristics of HBTs produced by changing the rate of temperature rise in the heat treatment. From Table 3, it can be said that the heating rate is preferably 10 ° C. or more per minute.

[0033]

[Table 3]

(Embodiment 2) Next, a second embodiment will be described with reference to FIG. In the multilayer structure shown in the first embodiment, n
N-type InGaP emitter layer and n-type InGaP emitter layer
By using the AlGaAs emitter layer instead of the two layers and stacking it to form a sidewall type self-alignment structure,
The distance between the side wall of the emitter mesa and the base electrode can be controlled.

On a semi-insulating GaAs substrate 201, an n ⁺ type GaAs
Collector contact layer 202, n-type InGaP etching stopper layer 203, n-type GaAs collector layer 204, p ⁺ -type G
aAs base layer 205, n-type InGaP emitter layer 206 (impurity concentration 5.0 × 10 ¹⁷ cm ⁻³ , film thickness 25 nm), n-type Al
GaAs emitter layer 207 (impurity concentration 5.0 × 10 ¹⁷ cm
^-3 , thickness 100 nm), n-type GaAs emitter layer 208, n
^{The +} type InGaAs emitter cap layer 209 is
Laminate by CVD. Even if a gas source MBE or the like is used, the layers can be similarly laminated.

On this substrate, a WN film serving as an emitter electrode is formed to a thickness of about 100 nm, the WN of the portion serving as the emitter is covered with a resist mask, and dry etching is performed to form the emitter in a ridge shape. At this time, by using a gas that does not etch InGaP, the InGaP emitter layer 20 is formed.
Etching stops when the surface of No. 6 is exposed. Next, a SiN film is deposited on the entire surface of the substrate by plasma CVD.
At this time, the InGaP emitter layer in the base electrode formation region is called an edge thinning layer.

Subsequently, the SiN film is dry-etched to form a sidewall 220. A portion other than a portion serving as an emitter electrode and a base electrode is covered with a resist, Pt / Ti / Pt / Au is deposited at a thickness of 10/50/50/60 nm, and a base electrode 211 and an emitter electrode 212 are formed by lift-off. Base electrode 211 is self-aligned by sidewall 220. Also, the side wall 220
, The distance between the emitter mesa side wall and the base electrode 211 can be set to 150 to 350 nm. Subsequently, the collector electrode 213 is made AuGe / Ni / Au by lift-off.
Is formed to a thickness of 100/15/100 nm. After that, a heat treatment is performed at 420 ° C. at a rate of temperature increase of 5 ° C./sec to form the base electrode 2.
11, the collector electrode 213 is the base layer 205,
An ohmic contact is made with the collector contact layer 202.
Thereafter, element separation is performed by etching or the like, an interlayer insulating film is formed, and wiring is formed by plating or vapor deposition.

The edge thinning layer containing InGaP may be a single layer of InGaP, or an AlGaAs layer, GaAs,
It may be a multilayer including layers. AlGaAs when an AlGaAs layer, GaAs layer, etc. are included between the InGaP layer and the base electrode
It is desirable that the thickness of the layer, the GaAs layer, and the like be 5 nm or less. In this embodiment, when the AlGaAs emitter layer is etched, it may be left in a thickness of 5 nm or less.

Table 4 shows the results of the device characteristics when the distance between the emitter mesa side wall and the base electrode was changed. Table 4 shows that the distance between the side wall of the emitter mesa and the base electrode is 150 to 35.
It can be said that 0 nm is preferable.

[0040]

[Table 4]

[0041]

According to the semiconductor device of the present invention, a good base ohmic contact can be obtained. In addition, a good collector contact can be made at the same time.
Even in a process including a long-term heat treatment at a temperature of 00 ° C. or more, diffusion of an electrode material into a semiconductor layer or an alloying reaction does not proceed, and a thermally stable and highly reliable compound semiconductor can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a compound semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a compound semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a schematic view showing a structure near a base electrode according to the first embodiment.

FIG. 4 is a cross-sectional view showing a structure of a conventional compound semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 semi-insulating GaAs substrate 102 GaAs collector contact layer 103 InGaP etching stopper layer 104 GaAs collector layer 105 GaAs base layer 106 InGaP emitter layer 107 GaAs emitter layer 108 InGaAs emitter cap layer 111 base electrode 112 emitter electrode 113 collector electrode 120 alloying region Reference Signs List 201 semi-insulating GaAs substrate 202 GaAs collector contact layer 203 InGaP etching stopper layer 204 GaAs collector layer 205 GaAs base layer 206 InGaP emitter layer 207 AlGaAs emitter layer 208 GaAs emitter layer 209 InGaAs emitter cap layer 211 base electrode 212 emitter electrode 213 collector electrode 220 Sidewall 221 Alloyed region 501 Collector layer 502 Base layer 503 Edge thinning layer 504 Base electrode 505 Alloyed region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F003 AP04 BA06 BA11 BA92 BB02 BE90 BF06 BF90 BH08 BH18 BH99 BM02 BP11 BP12 BP32 BP41 BS05

Claims (6)

[Claims] 1. A heterojunction bipolar transistor having a vertical structure in which at least a semiconductor layer of a collector contact layer, a collector layer, a base layer, and an emitter layer is sequentially laminated on a compound semiconductor substrate, wherein a base electrode and the base layer An edge thinning layer is provided between the base electrode and the collector layer, and the edge thinning layer includes an InGaP layer at a rate of 10.75 to 32.25 μg / cm ² per unit area between the base electrode and the collector layer.
A compound semiconductor device having a region containing t or 6.0 to 18.00 μg / cm ² of Pd. 2. The thickness of the edge thinning layer is 20-4.
2. The compound semiconductor device according to claim 1, wherein the thickness is 0 nm. 3. The emitter layer has a mesa shape, and a distance between an emitter mesa side wall and a base electrode is 150 to 350.
3. The compound semiconductor device according to claim 1, wherein 4. A method of manufacturing a heterojunction bipolar transistor having a vertical structure in which at least a semiconductor layer of a collector contact layer, a collector layer, a base layer, and an emitter layer is sequentially stacked on a compound semiconductor substrate, wherein a base electrode is formed. In the region to be etched, an edge thinning layer including at least an InGaP layer is formed by etching while leaving a part of the emitter layer, Pt or Pd having a thickness of 5 to 15 nm is deposited on the edge thinning layer, and heat treatment is performed. A method of diffusing Pt or Pd from the edge thinning layer to the base layer. 5. The method according to claim 4, wherein the heat treatment is performed at 420 ° C. or higher. 6. At the time of raising the temperature for performing the heat treatment, 25
6. The method of manufacturing a compound semiconductor device according to claim 5, wherein a temperature rising rate between 0 ° C. and 420 ° C. is 10 ° C. or more per minute.