JP2000357794A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent any short-circuit between the source/drain regions of N-channel MOS transistors which is caused by N-type reversals, as maintaining the desired characteristic of the high-withstanding-voltage N-channel MOS transistor, by providing separately from the N-type source/drain regions of the N-channel MOS transistors the regions of introducing P-type impurities thereinto. SOLUTION: Although the N-type reversals of the side surfaces of an element separating region can be generated in the four side surfaces of the element separating region of the portion partitioned by a P-type well region 2, by forming P-type diffusion layers 4 on the two side surfaces of the channel sides of two MOS transistors, the shorting path of N+-diffusion layers 3 intended to be source/drain regions is interrupted by the presences of the P-type diffusion layers 4 when the N-type reversals occur. Hereupon, it is important that each P-type diffusion layer 4 is provided separately by X from each N+-diffusion layer 3. When the former is not separated from the latter, because each P-type diffusion layer 4 having a higher impurity concentration than the P-type well region 2 contacts with each N+-diffusion layer 3, the withstading voltage of the junction of a high-withstanding-voltage transistor is reduced in this portion not to make obtainable its intrinsic characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an N-channel MO.
The present invention relates to a semiconductor device used as an S transistor.

[0002]

2. Description of the Related Art In general, CMOS Nch and Pch transistors used in large-scale integrated circuits (LSI) have been operating at lower voltages year by year, and their power consumption has been reduced.

However, in a flash memory device, which has been widely applied in recent years, a high voltage is required for writing / erasing charges in a memory cell. The write / erase voltage does not follow the scaling rule of the MOS transistor, but is simply determined by the tunnel oxide film thickness through which the charge at the time of write / erase passes and the write / erase time. Therefore, a high voltage of about ± 20 V is required depending on the writing / erasing method for the memory cell.

As a matter of course, a circuit for generating this high voltage or applying it to a memory cell requires a MOS transistor having a junction breakdown voltage and an insulation breakdown voltage that can withstand this high voltage. This high breakdown voltage transistor is basically the same as a low voltage transistor in its basic structure. However, when low voltage and high voltage MOS transistors are mixed in the same LSI chip, the size and diffusion layer impurity distribution are reduced. Will be different.

FIG. 7 is a top view of a conventional N-channel MOS high voltage transistor, and FIGS. 8 and 9 are cross-sectional views in which the direction of FIG. 7 is different.
OS transistor. However, an N-type well region 7 is provided below the P-type well region 2 so that a negative high voltage can be handled, and the lowermost layer is a P-type silicon substrate 8. Although the junction breakdown voltage of each region differs depending on the method of use in the LSI, for example, when it is desired to obtain a PN junction breakdown voltage of about 20 V between the N ⁺ diffusion layer 3 and the P-type well region 2, the P-type well region 2 The impurity concentration must be within 1E17 cm ³ .
Further, when the N-type well region 7 is formed under the P-type well region 2 in this state, the impurity concentration must be equal to or higher than the impurity concentration of the general P-type silicon substrate 8 of 1E16 cm ^3. The impurity concentration of the mold well region 7 needs to be the impurity concentration between the P-type well region 2 and the P-type silicon substrate 8.

[0006]

FIGS. 8 and 9 show an embodiment of the present invention.
In general, the method of manufacturing the element isolation region 5 includes a LOCOS isolation method of selectively oxidizing a silicon substrate and a groove isolation method of digging a trench and filling an insulator. In both cases, the interface with silicon is an oxide film. In addition, a phenomenon that boron of a P-type impurity is absorbed into the oxide film at the interface of the isolation region by segregation due to various oxidation treatments or the like during the LSI process is inevitable. In this case, boron is absorbed in the vicinity of the interface between the P-type well region 2 and the element isolation region 5 indicated by the bold line in FIGS. 8 and 9, so that the P-type impurity concentration becomes low and the N-type well region 7 is formed. The N-type impurity concentration (such as phosphorus) for the above may be higher, causing N-type inversion. FIG.
FIG. 0 shows a cross-sectional impurity distribution when N-type inversion occurs immediately below the element isolation region in FIG.

[0007] Such an N-type inversion is performed by an N-channel MO.
N ⁺ diffusion layer 3 as drain and source of S transistor
Is short-circuited (the thick line in FIG. 7), the boron concentration in the P-type well region 2 or the impurity concentration in the N-type well region 7 may be reduced. There is a danger of N-type inversion depending on the required breakdown voltage and process. It is well known that boron is added to the bottom portion of the element isolation region by ion implantation. However, a short circuit between the drain and source due to N-type inversion also occurs on the side surface of the element isolation region. The problem is not solved by boron ion implantation only at the bottom of the isolation region, and N-type inversion of the P-type well region is still a problem of the high breakdown voltage N-channel MOS transistor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and a semiconductor device capable of maintaining desired characteristics of a high breakdown voltage N-channel MOS transistor and preventing a short circuit of a source and a drain due to N-type inversion. The purpose is to provide.

[0009]

The present invention provides the following semiconductor devices (1) to (4) to achieve the above object.

(1) A P-type impurity is introduced into a part of a P-type well of an N-channel MOS transistor in contact with an interface between an element isolation region and a P-type well. A semiconductor device having a structure arranged away from N-type source and drain regions of a MOS transistor.

(2) The semiconductor device according to (1), wherein the region into which the P-type impurity is introduced is formed so as to be in contact with the entire vertical surface of the side surface of the element isolation region.

(3) The semiconductor device according to (1) or (2), wherein a boron compensation P-type region is formed on the bottom surface of the element isolation region.

(4) The semiconductor device according to any one of (1) to (3), wherein the P-type diffusion layer and the N-type source / drain regions are formed at a distance X = 0.5 μm or more.

That is, a feature of the present invention is that, in an N-channel MOS transistor, a P-type diffusion layer is formed in contact with a part of a side surface of an element isolation region.
This is because the MOS transistor is formed separately from the N ⁺ diffusion layer which is the source and drain of the MOS transistor.

[0015]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. 1, 2, and 3
The configuration of the embodiment will be described with reference to FIG. 2 and 3, in order to prevent a short circuit between the source and the drain (N ⁺ diffusion layer 3) due to N-type inversion at the side surface of the element isolation region 5,
As shown in FIG. 1, a P-type diffusion layer 4 is formed on two sides of a channel side surface of a MOS transistor in a P-type well region 2 so as to be in contact with an element isolation region. At this time, as shown in FIG. 3, the P
A mold diffusion layer 4 is formed. Since this portion has a high concentration of boron, N-type inversion is difficult to occur even if boron is absorbed into the silicon oxide film in the element isolation region by an oxidation step or the like. The P-type diffusion layer 4 and the N ⁺ diffusion layer 3 are formed apart from each other by a distance X. As shown in FIGS. 2 and 3, a boron compensation P-type region 9 for preventing N-type inversion is formed on the bottom surface of the element isolation region 5.

Next, the manufacturing process of the first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a process sectional view corresponding to a section taken along line aa ′ of FIG. 1, and FIG. 5 is a process sectional view corresponding to a section taken along line bb ′ of FIG. 4 (a) to 4 (c), FIG.
(A) to (c) are cross sections in the same step.

First, to obtain an impurity layer as shown in FIGS. 4A and 5A, an N-type well region 7 is formed in a P-type silicon substrate 8 by impurity vapor diffusion or ion implantation and heat treatment. I do. Subsequently, a P-type well region 2 is similarly formed.
In an LSI, a P-type silicon substrate is usually fixed to ground (0 V).
If the N-type well region 7 is inserted between the substrate and the P-type well region and is not set to 0 V or + potential, the N-type MOS transistor of the negative voltage operation having the P-type well region as a negative potential
The transistor stops operating. Next, N channel M
An N ⁺ diffusion layer 3 serving as a source and a drain of the OS transistor is formed. A recent general MOS transistor is
After forming the gate electrode pattern, the source and
The drain diffusion layer is formed, but is formed first in the present invention.

Next, as shown in FIGS. 4 (b) and 5 (b),
An element isolation region 5 is formed. Recently, after digging a trench, a silicon oxide film-based insulator is buried and flattened.
A TI (Shallow Trench Isolation) structure has been used. At this time, the boron compensation P-type region 9 shown in FIGS. 4 and 5 is formed by selectively implanting boron ions into the N-type well region immediately after the trench is dug.
Thus, N-type inversion due to the absorption of boron into the element isolation region 5 can be prevented at the bottom surface of the element isolation region 5. Further, as shown in FIG. 5B, the P-type diffusion layer 4 is selectively formed by introducing boron only into the portion shown in FIG. At this time, it is important that the depth of the P-type diffusion layer 4 is equal to or greater than the depth of the element isolation region 5, and that the side surface of the element isolation region is completely covered with the P-type diffusion layer in the depth direction. Further, the boron concentration in the P-type diffusion layer region depends on the amount of boron absorbed into the element isolation region 5, but a dose higher than that is required.

Next, as shown in FIGS. 4 (c) and 5 (c),
The gate oxide film 6 and the polycrystalline silicon gate 1 are
It may be formed in accordance with the OS transistor process. Through the above steps, all the structures of the present invention shown in FIGS. 1 to 3 are formed.

The effects of the present invention will be described with reference to FIGS. 1, 2 and 3. Referring to FIG. 7, the N-type inversion of the side surface of the element isolation region, which is the subject of the present invention, can occur on the four side surfaces (FIGS. 8 and 9) of the element isolation region 5 defined by the P-type well region 2. However, as shown in FIG.
By forming the P-type diffusion layer 4 on the two channel-side sides of the transistor, a short-circuit path of the N ⁺ diffusion layer 3 serving as a source and a drain when N-type inversion occurs due to the presence of the P-type diffusion layer 4 Will be shut off.

It is important that the P-type diffusion layer 4
And the N ⁺ diffusion layer 3 are separated by X in FIG. If they are not separated from each other, the P-type diffusion layer 4 having a higher impurity concentration than the P-type well region 2 comes into contact with the N ⁺ diffusion layer, and the junction breakdown voltage is reduced at this portion. I can't. Therefore, as shown in FIG.
Must be separated by a distance of

The value of X is determined as follows. That is, in the portion of X, the N-type impurity concentration in the case of N-type inversion is lower than the concentration of the surface portion of the original N-type well region from the impurity distribution diagram of FIG. 10 (indicated by phosphorus in FIG. 10). . As described above, the N-type concentration is equal to or higher than the concentration of the P-type silicon substrate 8 and lower than the concentration of the P-type well region 2, that is, 1E1 when an element with a withstand voltage of 20 V is required.
A 7cm ³ within in 1E16cm ³ or more. With this concentration, a junction withstand voltage of about 20 V can be sufficiently obtained even when in contact with the P-type diffusion layer 4. However, when the distance of X is short, a depletion layer extending from the junction with the P-type diffusion layer 4 to the N-type inversion portion is N ⁺
Reaching the diffusion layer, the junction withstand voltage is reduced due to the effective reduction of the depletion layer width. Therefore, when the N-type inversion concentration becomes 1E17 cm ^{3 at the} worst, the depletion layer width at a voltage of 20 V is calculated to be about 0.5 μm. Therefore, if X = 0.5 μm or more, the depletion layer extends sufficiently,
The junction breakdown voltage does not decrease due to the presence of the P-type diffusion layer 4, and the short circuit of the source and the drain (N ⁺ diffusion layer 3) due to N-type inversion can be prevented while maintaining the desired characteristics of the high breakdown voltage MOS transistor.

Next, the manufacturing process of the second embodiment of the present invention will be described with reference to FIG. FIGS. 6 (a) to 6 (c) correspond to FIGS.
It is a process sectional view corresponding to the -b 'section. This embodiment is different from the first embodiment in the position of the step of forming the P-type diffusion layer. That is, in the first embodiment, the P-type diffusion layer 4 is formed after the formation of the element isolation region 5, but in the second embodiment, it is formed before the formation of the element isolation region.

First, an N-type well region 7 and a P-type well region 2 are formed on a P-type silicon substrate 8 shown in FIG. Up to this point, the operation is the same as in the first embodiment. Then, P
The type diffusion layer 4 is selectively formed as shown in FIG. 6A in accordance with a portion where an element isolation region will be formed in the future. At this time, the portion where the P-type diffusion layer is formed has a margin on the element isolation region side (outside the P-type well region in FIG. 1) slightly from the region of the P-type diffusion layer 4 shown in FIG. It may be formed larger. Thereafter, an element isolation region 5 and a boron compensation P-type region are formed as in the first embodiment (FIG. 6B). Finally, as in the first embodiment, the gate oxide film 6 and the polysilicon gate 1 are formed. May be formed according to a normal MOS transistor process.

[0025]

As described above, according to the semiconductor device of the present invention, while maintaining the desired characteristics of the high breakdown voltage N-channel MOS transistor, the source and drain (N
⁺ Short circuit of the diffusion layer 3) can be prevented.

[Brief description of the drawings]

FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line a-a 'of the semiconductor device of FIG.

FIG. 3 is a sectional view taken along line b-b 'of the semiconductor device of FIG. 1;

FIG. 4 is a process sectional view corresponding to a section taken along line aa ′ of FIG. 1, illustrating the manufacturing process of the first embodiment of the present invention.

FIG. 5 is a process sectional view corresponding to a section taken along line bb 'of FIG. 1, showing the manufacturing process of the first embodiment of the present invention.

FIG. 6 is a process sectional view corresponding to a section taken along line bb 'of FIG. 1, showing the manufacturing process of the second embodiment of the present invention.

FIG. 7 is a top view illustrating an example of a conventional semiconductor device.

FIG. 8 is a sectional view taken along line a-a ′ of the semiconductor device of FIG. 7;

9 is a cross-sectional view of the semiconductor device of FIG. 7 taken along line b-b '.

FIG. 10 is an impurity distribution diagram for explaining the problem of the conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 polycrystalline silicon gate 2 P-type well region 3 N ⁺ diffusion layer 4 P-type diffusion layer 5 element isolation region 6 gate oxide film 7 N-type well region 8 P-type silicon substrate 9 boron-compensated P-type region

Claims (4)

[Claims] A P-type impurity is introduced into a part of a P-type well of an N-channel MOS transistor in contact with an interface between an element isolation region and a P-type well. The N-type source of the transistor,
A semiconductor device having a structure arranged apart from a drain region. 2. The semiconductor device according to claim 1, wherein the region into which the P-type impurity is introduced is formed so as to be in contact with the entire vertical surface of the side surface of the element isolation region. 3. The semiconductor device according to claim 1, wherein a boron compensation P-type region is formed on a bottom surface of the element isolation region. 4. The semiconductor device according to claim 1, wherein the P-type diffusion layer and the N-type source / drain regions are formed at a distance X = 0.5 μm or more.