JP2000514602A - 高ドーピングされた領域に対して低い接触抵抗を有する半導体構成要素の製造方法 - Google Patents
高ドーピングされた領域に対して低い接触抵抗を有する半導体構成要素の製造方法Info
- Publication number
- JP2000514602A JP2000514602A JP10505507A JP50550798A JP2000514602A JP 2000514602 A JP2000514602 A JP 2000514602A JP 10505507 A JP10505507 A JP 10505507A JP 50550798 A JP50550798 A JP 50550798A JP 2000514602 A JP2000514602 A JP 2000514602A
- Authority
- JP
- Japan
- Prior art keywords
- titanium
- layer
- highly doped
- contact hole
- semiconductor component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. −マスク層(3)における接点穴(4)を介して半導体部材(1)にn+− 又はp+−導電する高ドーピングされた又はケイ化された領域(2)を製造し、 −高ドーピングされた又はケイ化された領域(2)の表面範囲(5)において接 点穴(2)の範囲にふっ素イオンを注入し、かつ −続いて接点穴(4)内にチタンを含む少なくとも1つの層(6,7)をコーテ ィングし、かつ接点金属(8)を取付ける 方法ステップを有する、半導体構成要素の製造方法。 2. ふっ素を、1012ないし1016イオン/cm2の計量により注入することを特 徴とする、請求項1に記載の方法。 3. ふっ素を、5ないし50keVのエネルギーによって注入することを特徴と する、請求項1又は2に記載の方法。 4. チタンを含む層を製造するために、チタン膜(6)及びその上に窒化チタン 膜(7)をコーティングすることを特徴とする、請求項1から3までの1つに記 載の方法。 5. 10ないし100、とくに40nmの層厚を有す るチタン膜(6)をコーティングすることを特徴とする、請求項4に記載の方法 。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19628459.7 | 1996-07-15 | ||
| DE19628459A DE19628459A1 (de) | 1996-07-15 | 1996-07-15 | Halbleiterbauelement mit niedrigem Kontaktwiderstand zu hochdotierten Gebieten |
| PCT/DE1997/001461 WO1998002914A1 (de) | 1996-07-15 | 1997-07-10 | Halbleiterbauelement mit niedrigem kontaktwiderstand zu hochdotierten gebieten |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000514602A true JP2000514602A (ja) | 2000-10-31 |
Family
ID=7799860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10505507A Pending JP2000514602A (ja) | 1996-07-15 | 1997-07-10 | 高ドーピングされた領域に対して低い接触抵抗を有する半導体構成要素の製造方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6232220B1 (ja) |
| EP (1) | EP0912995B1 (ja) |
| JP (1) | JP2000514602A (ja) |
| KR (1) | KR100421300B1 (ja) |
| DE (2) | DE19628459A1 (ja) |
| TW (1) | TW382751B (ja) |
| WO (1) | WO1998002914A1 (ja) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5620906A (en) * | 1994-02-28 | 1997-04-15 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device by introducing hydrogen ions |
| JP3534668B2 (ja) * | 1998-11-20 | 2004-06-07 | セイコーインスツルメンツ株式会社 | 半導体集積回路 |
| TW522513B (en) * | 2001-10-09 | 2003-03-01 | Winbond Electronics Corp | Manufacturing method of self-aligned silicide for metal oxide semiconductor transistor |
| US7439123B2 (en) * | 2005-10-31 | 2008-10-21 | International Business Machines Corporation | Low resistance contact semiconductor device structure |
| CN112188903A (zh) * | 2018-06-01 | 2021-01-05 | 京瓷株式会社 | 复合材料及生物体植入物 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2645088B2 (ja) * | 1988-07-15 | 1997-08-25 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2947818B2 (ja) * | 1988-07-27 | 1999-09-13 | 株式会社日立製作所 | 微細孔への金属穴埋め方法 |
| US5296386A (en) * | 1991-03-06 | 1994-03-22 | National Semiconductor Corporation | Method of providing lower contact resistance in MOS transistor structures |
| JP2672199B2 (ja) * | 1991-05-21 | 1997-11-05 | シャープ株式会社 | 半導体装置の製造方法 |
| JP2834344B2 (ja) * | 1991-07-17 | 1998-12-09 | シャープ株式会社 | 半導体装置の絶縁膜の製造方法 |
| US5225357A (en) * | 1992-01-02 | 1993-07-06 | Chartered Semiconductor Manufacturing | Low P+ contact resistance formation by double implant |
| US5466612A (en) * | 1992-03-11 | 1995-11-14 | Matsushita Electronics Corp. | Method of manufacturing a solid-state image pickup device |
| US5580808A (en) * | 1992-07-30 | 1996-12-03 | Canon Kabushiki Kaisha | Method of manufacturing a ROM device having contact holes treated with hydrogen atoms and energy beam |
| JPH07249763A (ja) | 1994-03-09 | 1995-09-26 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2621821B2 (ja) * | 1995-03-06 | 1997-06-18 | 日本電気株式会社 | 半導体記憶装置の容量素子の製造方法 |
| US5591672A (en) * | 1995-10-27 | 1997-01-07 | Vanguard International Semiconductor Corporation | Annealing of titanium - titanium nitride in contact hole |
| US5605848A (en) * | 1995-12-27 | 1997-02-25 | Chartered Semiconductor Manufacturing Pte Ltd. | Dual ion implantation process for gate oxide improvement |
| TW385523B (en) * | 1996-12-14 | 2000-03-21 | United Microelectronics Corp | Method for making contact via with a formed component on semiconductor substrate |
-
1996
- 1996-07-15 DE DE19628459A patent/DE19628459A1/de not_active Ceased
-
1997
- 1997-06-19 TW TW086108568A patent/TW382751B/zh not_active IP Right Cessation
- 1997-07-10 EP EP97933624A patent/EP0912995B1/de not_active Expired - Lifetime
- 1997-07-10 JP JP10505507A patent/JP2000514602A/ja active Pending
- 1997-07-10 DE DE59707373T patent/DE59707373D1/de not_active Expired - Lifetime
- 1997-07-10 WO PCT/DE1997/001461 patent/WO1998002914A1/de not_active Ceased
- 1997-07-10 KR KR10-1999-7000231A patent/KR100421300B1/ko not_active Expired - Lifetime
-
1999
- 1999-01-15 US US09/232,868 patent/US6232220B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0912995A1 (de) | 1999-05-06 |
| US6232220B1 (en) | 2001-05-15 |
| WO1998002914A1 (de) | 1998-01-22 |
| DE59707373D1 (de) | 2002-07-04 |
| KR100421300B1 (ko) | 2004-03-10 |
| EP0912995B1 (de) | 2002-05-29 |
| KR20000023765A (ko) | 2000-04-25 |
| DE19628459A1 (de) | 1998-01-29 |
| TW382751B (en) | 2000-02-21 |
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