JP2003036070A - Image conversion method and image conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a real-time image transform process using DRAMs. SOLUTION: An image memory 3 comprises the DRAMs having a bank structure. When an input image data is written into the image memory 3, the bank is switched each time one line of the input image data is written. When the image data is read from the image memory 3, the bank is switched each time one pixel of the image data is read. The image transform process for the input image data can be performed without random access to the image memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image conversion method and an image conversion device for converting an input image into a display image rotated by 90 °.

[0002]

2. Description of the Related Art In recent years, image display devices represented by television receivers and computer displays have been widely used in various electronic devices such as portable video cameras and car navigation devices.

[0003]

By the way, most of the image display devices up to now are of the stationary type, and usually the screen orientation thereof is fixed. On the other hand, in recent years, portable image display devices that are widely used have various usage forms, and it is naturally expected that the image display device will be used, for example, in a state where the screen orientation is rotated by 90 °. Therefore, for example, in a portable image display device, it is naturally preferable to be able to perform an image conversion process of rotating a display image in accordance with the orientation of the screen.

For example, in an image display device, to display the input moving image data by rotating it by 90 °, for example,
It is required to perform the image conversion processing in real time. In the image display devices up to now, the image conversion process is mainly performed by using the image memory. Therefore, it is structurally preferable that the rotation process of the moving image data as described above is also performed by using the image memory. Become. However, when the rotation processing of moving image data as described above is performed using the image memory, a data writing operation to the image memory,
Alternatively, a random access operation is required for the data read operation, and its processing speed becomes a problem.

Therefore, as one means for performing image conversion processing of input moving image data in real time, for example, a static random access memory (SRAM: Static Random Acce
It may be configured by ss Memory).

However, each SRAM has a small memory capacity and is very expensive.
For this reason, when the image memory that requires a relatively large memory capacity is configured by, for example, an SRAM, a plurality of SRAMs are required, which is very expensive. Further, since the SRAM consumes a relatively large amount of power, if an image memory is configured using a plurality of SRAMs, power consumption will increase.

Therefore, in comparison with, for example, SRAM, the memory capacity per unit is large and the power consumption is small, and
Inexpensive dynamic random access memory (DR
It is conceivable to configure the image memory by AM (Dynamic Random Access Memory).

However, the access speed of the DRAM is random access in which the memory area is randomly accessed as compared with the so-called burst access speed in which high-speed access is enabled by sequentially accessing the memory area. Since the time speed is about 7 to 8 times slower, it is difficult to perform the rotation processing of moving image data in real time when the image memory is composed of DRAM.

[0009]

In view of the above points of the present invention, an image conversion process of moving image data is performed in S.
An object of the present invention is to provide an image conversion method and an image conversion device that can be performed in real time without using a RAM.

In order to achieve the above object, the image conversion method of the present invention for converting an input image into a predetermined output image, when input image data is written in a storage means having a plurality of data storage areas, Each time the input image data for one line is written in the data storage area by the burst write operation, the data storage areas are sequentially switched, and the same write address is set between the data storage areas during the cycle of switching the data storage areas. When performing the designated write procedure and reading the output image data from the data storage area, the data storage area is sequentially switched every time one pixel of image data is read from the data storage area, and During one cycle of storage area switching, the same read address is specified between data storage areas. And a read procedure which is adapted to have to be executed.

An image conversion apparatus for converting an input image into a predetermined output image according to the present invention includes a storage unit having a plurality of data storage areas, and one line in the data storage area when writing the input image data. Each time the minute input image data is written by the burst write operation, the data storage area is switched, and during the switching of the data storage area, the same write address is designated between the data storage areas. Means and
When the output image data is read from the data storage area, the data storage area is switched every time one pixel of image data is read from the data storage area, and while the switching of the data storage area is complete, And a read means adapted to specify the same read address between the data storage areas.

According to the present invention as described above, every time one line of input image data is written in the data storage area,
While the data storage areas are switched, the same write address is designated between the data storage areas while the data storage areas are switched. Then, every time one pixel of image data is read from the data storage area,
While switching the data storage area, by designating the same read address between the data storage areas during this cycle of switching the data storage area, the input image can be input by a faster access operation than the conventional random access operation. Image data conversion processing becomes possible.

Further, according to the image conversion method of the present invention for converting an input image into a predetermined output image, when the input image data is written in the storage means having a plurality of data storage areas, it is set to 1 in the data storage area. Each time the input image data for a pixel is written, the data storage area is switched, and during the switching of the data storage area, a writing procedure that specifies the same write address between the data storage areas, When reading output image data from the data storage area,
Each time the output image data for a line is read by the burst read operation, the data storage area is switched, and the same read address is designated between the data storage areas during the cycle of switching the data storage area. The read procedure and are executed.

Further, the image conversion apparatus of the present invention for converting an input image into a predetermined output image has a storage means having a plurality of data storage areas, and when writing the input image data, 1 is stored in the data storage area. Each time the input image data for a pixel is written, the data storage area is switched, and during the switching of the data storage area, a writing means configured to specify the same write address between the data storage areas, When reading output image data from the data storage area,
Each time the output image data for a line is read by the burst read operation, the data storage area is switched, and the same read address is designated between the data storage areas during the cycle of switching the data storage area. Read-out means.

According to the present invention as described above, the data storage area is switched every time one pixel of input image data is written in the data storage area, and the data storage area is switched during one cycle. Specify the same write address between storage areas. Then, every time one line of image data is read from the data storage area,
While switching the data storage area, by designating the same read address between the data storage areas during this cycle of switching the data storage area, the input image can be input by a faster access operation than the conventional random access operation. Image data conversion processing becomes possible.

[0016]

1 is a block diagram showing a configuration of an image conversion apparatus and its peripheral circuits according to an embodiment of the present invention. In FIG. 1, an A / D converter (hereinafter, referred to as “ADC”) 1 converts an analog input image signal input from a pre-stage circuit (not shown) into digital input image data and outputs the digital input image data.

The memory controller 2 performs write operation control for writing the input image data from the ADC 1 into the image memory 3 and read operation control for reading the image data from the image memory 3. At this time, the memory controller 2 controls the operation of the image memory 3 based on the horizontal synchronizing signal H, the vertical synchronizing signal V, and the clock CLK that are input from the preceding circuit (not shown).
The operation control performed by the memory controller 2 on the image memory 3 will be described later.

The image memory 3 is, for example, a large capacity SDRA.
M (Synchronous Dynamic Random Access Memory) or DDR SDRAM (Double Data Rate Synchrono)
us Random Access Memory), FCRAM (Fast Cycle)
Random Access Memory) and the like, and the inside thereof is divided into a plurality of data storage areas, so-called banks (Ba
nk) structure.

The bank structure of the image memory will be briefly described with reference to FIG. FIG. 2 is a diagram schematically showing the structure of an SDRAM having a so-called four-bank structure in which the internal data storage area is divided into four banks (A, B, C, D). In this case, each bank A to D of the SDRAM which is the image memory 3 has a column direction (col).
256 in the umn direction and 2 in the row direction (Row direction)
It is assumed that 048 data can be stored.
That is, 256 × 2048 data can be stored in one bank, and the entire SDRAM has 256 × 2 data.
It is possible to store 048 × 4 data.

The D / A converter (DAC) 4 shown in FIG.
Converts the image data read from the image memory 3 into an analog image signal and outputs the analog image signal to the matrix circuit 5.
The matrix circuit 5 converts the image signal from the DAC 4 into three primary color signals (R, G, B) and outputs them. Then, the three primary color signals (R, G,
B) is a display device via a drive circuit (not shown), for example, a cathode ray tube (CRT) 6
And will be displayed as an image. In addition,
In the present embodiment, the CRT 6 is illustrated as a display device, but this is merely an example, and it goes without saying that the display device can be configured by another display device such as a liquid crystal display or a plasma display.

The sync signal generator 7 generates a horizontal / vertical sync signal for output from the horizontal sync signal H, the vertical sync signal V, and the clock CLK input from the preceding circuit (not shown), and the deflection circuit 8 of the CRT 6 is generated. Output to. The deflection circuit 8 is
Deflection scanning in the horizontal and vertical directions is performed based on the horizontal / vertical synchronizing signal for output from the synchronizing signal generator 7.

In the image conversion apparatus of this embodiment, the memory controller 2 controls the operation of the image memory 3 as will be described later to output the output image data obtained by rotating the input image data by 90 °. To get
Image conversion processing is performed such that the input image is rotated by 90 ° and displayed.

Hereinafter, an example of image conversion that can be realized by the image conversion apparatus of this embodiment will be described. In the image conversion example described below, it is assumed that the image memory 3 of the image conversion device is composed of a 4-bank SDRAM.

Here, in the image conversion apparatus of the present embodiment, the number of pixels of image data forming one frame image is 4
80 pixels (dot) × 480 pixels (dot). Normally, one field (or one frame) of input image data is transmitted from left to right and then from top to bottom. Therefore, the deflection scanning of the image display device is performed by a predetermined number of horizontal scannings within one vertical scanning period. It is horizontal deflection scanning for scanning. Therefore, in the image conversion apparatus of the present embodiment, when converting an input image as shown in FIG. 3A into an output image rotated clockwise by 90 ° as shown in FIG. 3B, It suffices to convert the input image data whose pixel coordinates are as shown in FIG. 3C into output image data as shown in FIG. 3D. Hereinafter, the first and second image conversion examples will be described based on the relationship between the pixel coordinates of the input image data and the output image data.

<First Image Conversion Example> First, a first image conversion example will be described with reference to FIGS. First
In the image conversion example of, when writing the input image data into the image memory 3, every time one line of the input image data is written into the image memory 3, for example, the bank is bank A → bank B → bank C → bank D → bank. The order of switching is A → ...

Image memory 3 according to the first image conversion example
The procedure for writing the image data into the memory is as shown in FIG. That is, 1 of the input image data is stored in bank A.
Pixel data (1,1) to (1,48) corresponding to the line
0) is written, the bank is switched and bank B is set to 2
Pixel data (2,1) to (2,48) corresponding to the line
Write 0). Then, when the writing of the bank B is completed, the bank is switched, the pixel data (3, 1) to (3, 480) corresponding to the third line is written in the bank C, the bank is switched again, and the bank D is set to 4 lines. Pixel data (4,1) to (4,480) corresponding to the eyes
To write. Then, when the writing in the bank D is completed, the mode is switched to the bank A, and the pixel data (5, 1) to (5, 480) corresponding to the fifth line are written in the bank A.

Finally, the pixel data corresponding to the first line, the fifth line, ... 477th line of the input image data is written in the bank A, and the second line, the sixth line, ... ..Pixel data corresponding to the 478th line is written, pixel data corresponding to the 3rd line, 7th line ... 479th line is written to the bank C, and 4th line and 8th line to the bank D .... 480
Pixel data corresponding to the line line is written.

At this time, the input image data for one line is input to each of the banks A to D from the head position in the column direction (col).
Write in the (umn direction). However, in this case, since only 256 pixels of data can be written in the row direction of each bank A to D, the input image data for one line is stored in the memory for two rows (Row) of each bank A to D. I am trying to write using the area. in this case,
Pixel data for 256 pixels is written in a column having a higher address, and pixel data for the remaining 224 pixels is written in a column having a lower address. In this case, in the lower column, 32 pixels (256 pixels−224 pixels = 32 pixels)
Although the memory area of (pixels) is left, data is not written in the memory area.

In the first image conversion example, the image memory 3
When the output image data is read from, the bank is switched in the order of, for example, bank D → bank C → bank B → bank A every time one pixel of pixel data is read from the image memory 3.

The procedure for reading the image data according to the first image conversion example is shown in FIG. In this case, for example, every time pixel data for one pixel is read from the image memory 3, for example, bank D → bank C → bank B →
By reading the pixel data while switching banks in the order of bank A, output image data obtained by rotating the input image data by 90 ° is obtained. That is, FIG.
From the input image data shown in (c), FIG.
The output image data as shown in FIG.

The control operation executed by the memory controller 2 in order to realize the write operation and read operation of the first image conversion example described above will be described with reference to FIGS. 6 and 7.

FIG. 6 is a diagram showing the operation timing when the input image data for two lines is written in the image memory 3. In this case, the memory controller 2 outputs various commands for controlling the operation of the image memory 3 based on the input clock CLK. First, the command output from the memory controller 2 to the image memory 3 will be described. The command output from the memory controller 2 to the image memory 3 includes a control command for controlling the operation of each bank, a bank address for specifying the bank, and a row address (Row address for specifying the memory area of each bank). Address) and column address (column address).

The control command includes an active command "ACTV" for putting the bank into an operating state, a write command "WRITE" for writing data, a write auto precharge command "WRITEAUTO", and a read command "reading data". READ ”and read auto precharge command“ READOUT
O ”, a precharge command“ PREALL ”for refreshing all banks, and the like.

In this specification, the bank address value of bank A is "0", the bank address value of bank B is "1", the bank address value of bank C is "2", and the bank address value of bank D is "2". 3 ”. Then, based on these bank address values, the memory controller 2
The bank addresses output to the image memory 3 by "Ba A (00)", "Ba B (01)",
Notated as “Ba C (10)” and “BaD (11)”.

The address value x of each bank A, B, C, D in the column direction (column direction) is set to "0 to 255".
And the address value y in the row direction (row direction) of the banks A, B, C, D is set to "0 to 2047". Then, based on these column address values x, the row addresses output from the memory controller 2 to the image memory 3 are respectively set to "Co
l Ax "," Col Bx "," Col Cx "," C
ol Dx ”, and the row addresses output from the memory controller 2 to the image memory 3 based on the column address value y are“ RowAy ”,“ Row By ”, and
Notated as “Row Cy” and “Row Dy”.

When the writing operation to the image memory 3 according to the first image conversion example is performed, the memory controller 2 first, as shown in FIG. 6, various control commands and column addresses at the falling timing of the clock CLK. , Output the row address. For example, pixel data (1, 1) to (1, 1) corresponding to the first line of the input image data shown in FIG.
480) to the bank A, the active command “AC
"TV", the bank address "Ba A (00)", and the row address "Row A0" are output. Then, after one clock CLK has been delayed due to the operational limitation of the image memory 3 (denoted as “NOP” in the drawing), the write command “WR
ITE ”, the bank address“ Ba A (00) ”and the column address“ Col A0 ”are output. As a result, the first pixel data (1, 1) input as the input image data Din is written in the memory area of the bank A designated by the column address “Col A0” and the row address “Row A0”. .

Thereafter, the memory controller 2 writes the write command "WR" at the timing of the input clock CLK.
ITE ”and bank address“ Ba A (00) ”along with the column address“ Co
By outputting “A1” → “Col A2” ...
Row address "Row A0" and column address "Col A
Pixels corresponding to pixel coordinates (1, 2), (1, 3), ..., Which are input as input image data Din in the memory area of the bank A designated by “1”, “Col A2” ... Data is written, and finally the row address "R
ow A0 "and column addresses" Col A1 "to" Col
To all memory areas specified by "A255"
Input pixel data Din of pixel coordinates (1, 1) to (1, 256) is written.

Then, the input image data D is written in all the memory areas designated by the row address "Row A0".
When in is written, the precharge command "PR
By outputting "EALL", the writing operation of the pixel data Din to the memory area of the row address "Row A0" of the bank A is completed.

Then, at the timing of the next clock CLK,
The active command "ACTV", the bank address "Ba A (00)", and the row address "Row A1" are output again, and after one clock CLK, the write command "W
RITE ”, bank address“ Ba A (00) ”, and column address“ Col A1 ”are output. As a result, the input image data Din corresponding to the pixel coordinates (1,257)
Are written in the memory area of the bank A designated by the column address “Col A0” and the row address “Row A1” of the bank A.

Then, at the next timing of the clock CLK, the write command "WRITE" and the bank address "Ba"
A (00) ”and the column address“ Col A1 ”→“ Col A2 ”...
By sequentially outputting “Col A233”, the remaining pixel data (1, 25
7) to (1,480) are written in the bank A.

After the pixel data of the first line of the input image data is written in the bank A as described above, the precharge command "PREALL" is output again,
The writing operation of the pixel data Din to the memory area of the row address “Row A1” of the bank A is completed. Then, in order to write the pixel data of the second line to the bank B, the active command “ACTV”, the bank address “Ba B (01)” of the bank B, and the row address “Row B0” of the bank B are output again. . And after that,
The input image data is written in the bank B at the same operation timing as the writing in the bank A described above. Then, when the writing to the bank B is completed, the input image data on the third and fourth lines are written to the bank C and the bank D at the same operation timing as the writing to the bank A, respectively. Finally, the input image data for one frame is written in the banks A to D of the image memory 3 at the same operation timing.

When the input image data is written in the image memory 3 in this way, as can be seen from FIG.
Then, the image can be written in the image memory 3. That is, in this case, the write operation to the image memory 3 can be a high-speed burst access operation.

FIG. 7 is a diagram showing the operation timing when the input pixel data for one line is read from the image memory 3. In this case, the memory controller 2 needs to read the image data from the image memory 3 so that the output image data obtained by rotating the input image data by 90 ° can be obtained. That is, as shown in FIG.
0,1), (479,1) ... (1,1), (48
It is necessary to read the image data in the order of 0, 2) ... (1,480). Here, for example, pixel data (480, 1) written in each bank A to D of the image memory 3,
Focusing on (479, 1) ... (477, 1), it can be seen that these pixel data have the same row address and the same column address although they are in different banks. Then, other pixel data are written in the same manner. Therefore, pixel data for four pixels (480, 1),
When reading (479,1) ... (477,1),
It is sufficient to switch the banks in the order of D → C → B → A without changing the column address and the row address.
That is, if the banks are switched in the order of D → C → B → A for each pixel, it is understood that the column address or the row address may be changed each time the image data of four pixels is read.

Therefore, when the read operation according to the first image conversion example is performed, the memory controller 2 first performs the operation shown in FIG.
As shown in, after outputting the active command, row address, and bank address using 4 clocks CLK,
The next 4 clocks are used to output the read auto precharge command, column address, and bank address. As a result, pixel data for four pixels is read from the same address in banks D to A.
That is, in such a read operation, the image data for 4 pixels is read using 8 clocks CLK.

After that, the row address or the column address is changed at the operation timing corresponding to the input clock CLK, and the above-described read operation is performed, so that the input image data is finally obtained. The output image data for one frame rotated by 90 ° is read.

When the image data is read from the image memory 3 in this way, as can be seen from FIG. 7,
The image data for one pixel can be read from the image memory 3 with 2 clocks CLK.

That is, in the first image conversion example, when the input image data is written in the image memory 3, each time one line of the input image data is written in each of the banks A to D of the image memory 3, While switching between banks A to D,
While the banks A to D are switched once,
The same write address (row address and column address) is designated between the banks A to D. On the other hand, when the output image data is read from the image memory 3, each time one pixel of image data is read from the banks A to D, the banks A to D are read.
While D is switched, the same read address is designated in banks A to D during this cycle of bank A to D switching.

Therefore, if the output image data obtained by converting the input image data by 90 ° is obtained by the first image conversion example as described above, it is conventionally about 7 to 8 of the burst access.
The 90 ° image rotation process that required double access time can be performed in about twice the access time of burst access, so that it can be performed almost in real time even when using DRAM. Become. This makes it possible to convert input image data into output image data in real time, which is suitable for image conversion processing of moving image data.

FIG. 8 is a flow chart showing the processing operation executed by the memory controller 2 in order to perform the writing operation according to the first image conversion example described above. In addition,
In the following processing, the output timing of various commands output from the memory controller 2 to the image memory 3 is
The timing is set according to the clock CLK shown in FIG.

In this case, the memory controller 2 first sets the bank address value to "0", the row address value to "0", and the column address value to "0" in step S101.
Initialize to.

Next, in step S102, the memory controller 2 outputs the active command, the bank address, and the row address to put the bank A of the image memory 3 into the writable active state. Then, in the subsequent step S103, the write command, the bank address, and the column address are output. As a result, for example, the pixel data corresponding to (1, 1) of the input image data has the row address “Row A0” and the column address “Col A0”.
Write to the memory area of bank A specified by

Next, the memory controller 2 increments the column address value by 1 in step S104. Then, in the next step S105, it is determined whether or not the column address value is "256". Here, when a negative result is obtained, the process returns to step S103, and the processing is repeated from step S103.
For example, in the memory area of the row address “Row A0”, 25
Write data for 6 pixels.

If a positive result is obtained in step S105, the process proceeds to step S106, the column address value is initialized to "0", and the following step S10 is performed.
At 7, the precharge command is output at the timing according to the clock CLK. And the following step S10
8, the row address value is incremented by 1.

Then, in the next step S109, the active command, the bank address and the row address are output again, and in the subsequent step S110, the write command, the bank address and the column address are output. Then, in the next step S111, the column address value is set to 1
After the increment, in step S112, it is determined whether or not the column address value is "224".

Here, when a negative result is obtained, the process returns to step S110, and the process is repeated from step S110, so that, for example, the remaining 224 pixels of the first line are stored in the memory area of the row address "Row A1". Make sure to write the data.

Then, when a positive result is obtained in step S112, the process proceeds to step S113 and again,
The column address value is initialized to "0", and in the subsequent step S114, a precharge command is output.
Then, in the subsequent step S115, the bank address value is incremented by 1. That is, here, the processing for writing the input image data of the second line into the bank B is performed.

Then, in the next step S116,
It is determined whether the bank address value is "4", and if the bank address value is not "4", step S
Proceed to 118, decrement the row address value by 1, and proceed to step S119. Then, in step S119, it is determined whether or not the input image data for one frame has been written in the image memory 3, and if a negative result is obtained, the process is performed from step S102. If it is determined in step S116 that the bank address value is "4", the process proceeds to step S117.
The bank address value is initialized to "0" and the row address value is incremented by 1 to proceed to step S119. Then, when a positive result is obtained in step S119, the processing is ended assuming that the writing of the input image data for one frame is completed.

FIG. 9 is a flow chart showing the processing operation executed by the memory controller 2 in order to perform the read operation according to the first image conversion example described above. In addition,
Also in the following processing, the output timing of various commands output from the memory controller 2 to the image memory 3 is the timing corresponding to the clock CLK shown in FIG. 7.

In this case, the memory controller 2 first initializes the bank address value to "3", the row address value to "238", and the column address value to "0" in step S201.

Next, in step S202, the memory controller 2 outputs the active command, the bank address, and the row address to put the bank D of the image memory 3 into the readable active state.

Then, in the next step S203, the bank address is decremented by 1 and then in step S20.
4, it is determined whether or not the bank address value is "-1", and if a negative result is obtained, step S202
Then, the process from step S202 is repeated. Then, when a positive result is obtained in the following step S203, the process proceeds to step S205 to initialize the bank address value to "3", and then to the next step S2.
In 06, a read auto precharge command,
Outputs bank address and column address.

Then, in the next step S207, after decrementing the bank address by 1, the subsequent step S207
In 208, it is again determined whether or not the bank address value is “−1”, and when a negative result is obtained, the process returns to step S206 and the processing from step S206 is repeated. Such step S202
From the processing from step S207 to, for example, bank D
From the memory area corresponding to the row address value “238” and the column address value “0” of bank A, (480, 1) to (4
The data for four pixels (77, 1) are read out.

On the other hand, when a positive result is obtained in step S207, the process proceeds to step S209, the bank address value is initialized again to "3", and then the following step S2.
At 10, the row address value is decremented by 2. Then, in the next step S211, it is determined whether or not the row address value is smaller than "0", and when a negative result is obtained, the processing is performed from step S202. By performing such processing until a positive result is obtained in step S211, the output image data for one line is read.

On the other hand, when a positive result is obtained in step S211, the process proceeds to step S212, the column address value is incremented by 1, and then the following step S213.
In, the row address value is initialized to "238". Then, in the next step S214, it is determined whether or not the column address value is "256", and when a negative result is obtained, the pixel data of 480 lines, that is, the output image data of one frame is read in step S216. I am trying to judge whether or not. On the other hand, if a positive result is obtained in step S214, the row address value is incremented by 1 to set the initial value to "239" in step S215.
We will proceed to 16.

Then, when a negative result is obtained in step S216, the process returns to step S202 and the process is performed from step S202. Then, when a positive result is obtained in step S216, the process may be ended assuming that the reading of the output image data for one frame is completed.

<Second Image Conversion Example> Next, FIGS.
A second image conversion example will be described with reference to FIG.
The procedure for writing the image data in the image memory 3 according to the second image conversion example is shown in FIG.
That is, every time the input image data for one pixel is written in the bank of the image memory 3, the banks are switched in the order of bank A → bank B → bank C → bank D.

On the other hand, the procedure for reading the image data according to the second image conversion example is shown in FIG. In this case, every time one line of image data is read from the bank A of the image memory 3, bank A → bank B
→ Bank C → Bank D are switched in this order. Then, when the image data is read in the order of the banks A to D, the pixel data for one line is read from the bank A again in order. That is, the writing and reading procedure in the second image conversion example is the reverse of the writing and reading procedure in the first image conversion example described above.

Therefore, the operation timing at the time of writing in the second image conversion example is shown in FIG. 12, and the operation timing at the time of reading is shown in FIG. Figure 1
2 shows the operation timing when the input pixel data for one line is written in the image memory 3. In this case, as shown in FIG. Address and bank address are output. Then, the next four clocks are used to output the write auto precharge command, the column address, and the bank address. As a result, the pixel data corresponding to (1,1) to (1,4) are written in the memory area specified by the row address and the column address of the banks A to D. Therefore, in this case, FIG.
As can be seen from FIG. 2, the image data for 4 pixels can be written in the image memory 3 with 8 clocks CLK.

On the other hand, FIG. 13 shows the operation timing when the pixel data for two lines is read from the image memory 3, and in this case, the first line of the output image data rotated by 90 ° is shown. Corresponding pixel data (480,
In order to read 1) to (1, 1) from the bank A, data is read from the bank A at the timing of the clock CLK. Therefore, first, the clock CLK
At the timing of, the active command “ACTV”, the bank address “Ba A (00)”, and the row address “Ro
w A0 ”is output. Then, after one clock CLK, the read command "READ" and the bank address "B"
a A (00) ”and the column address“ Col A0 ”are output. As a result, the column address of the bank A "Col A
The data is read from the memory area specified by "0" and the row address "Row A0".

After that, at the timing of the input clock CLK, the read command “READ” and the bank address “Ba A (00)” are added together with the column address “Col A1” → “Col A1” in which the column address value is increased by one. A2 "
By outputting ..., the row address "Row A0"
And column address "Col A1", "Col A2" ...
Pixel data is read from the memory area of bank A designated by, and finally the row address "Ro
w A0 ”and column addresses“ Col A1 ”to“ Col ”
Data is read from the memory area designated by "A255".

Then, when the data is read from all the memory areas of the row address "Row A0", the precharge command "PREA" is used by using the three clocks CLK.
The row address of the bank A "Row"
Reading of data from the memory area "A0" is completed.

Then, at the next clock CLK timing,
Again, the active command "ACTV", the bank address "Ba A (00)", and the row address "Ro of bank A"
w A1 ”and at the timing of the next clock CLK, the read command“ READ ”, the bank address“ Ba A (00) ”of the bank A, and the column address“ Co
1 A1 ”is output. After that, by increasing the column address value of the bank A by 1, the remaining image data of the output image data of the first line is read, as can be seen from the above description. Then, when the output image data of the first line is read out, the output image data of the second line and subsequent lines are read out from each bank at the same operation timing as the read operation described above.
Data is read from each bank.
If the output image data is read from the image memory 3 in this way, as can be seen from FIG. 13, the data for one pixel can be read out with almost one clock CLK. That is, in this case, the read operation from the image memory 3 can be the burst access operation.

That is, if the image conversion is performed by such a second image conversion example, the input image data is converted into the image memory 3
When writing to, the data for 1 pixel is 2 clock CLK
It is possible to write the data for each pixel, and when reading the pixel data from the image memory 3, it is possible to read the data for one pixel with almost one clock CLK.

As described above, in the second image conversion example, when the input image data is written in the image memory 3, every time one pixel of the input image data is written in each of the banks A to D of the image memory 3. Further, the banks A to D are switched, and the same write address (row address and column address) is designated between the banks A to D while the banks A to D are switched once. On the other hand, when the output image data is read from the image memory 3, the banks A to
Every time one line of image data is read from D, the banks A to D are switched, and the same read address is designated in the banks A to D while the banks A to D are switched once. There is.

Therefore, even when the output image data obtained by converting the input image data by 90 ° is obtained by the second image conversion example as described above, or when the DRAM is used, 90 ° is obtained.
The image rotation processing of can be performed in almost real time. This makes it possible to convert input image data into output image data in real time, which is suitable for image conversion processing of moving image data.

FIG. 14 is a flow chart showing the processing operation executed by the memory controller 2 in order to perform the write operation according to the second image conversion example described above. In the following processing, the output timing of various commands output from the memory controller 2 to the image memory 3 is set to the timing corresponding to the clock CLK shown in FIG. In this case, the memory controller 2 initializes the bank address value to "0", the row address value to "1", and the column address value to "223" in step S301. Next, in step S302, the active command, bank address, and row address are output. Then, in the next step S303, after incrementing the bank address by 1, in the following step S304,
It is determined whether or not the bank address value is "4", and when a negative result is obtained, the process returns to step S302 and the processing from step S302 is repeated. When a positive result is obtained in step S303, the process proceeds to step S305, the bank address value is initialized to "0", and then in step S306, the write auto precharge command, the bank address, and the column address are read. Is output.

Then, in the next step S307, the bank address is incremented by 1, and then in the following step S308, it is determined again whether or not the bank address value is "4". If a negative result is obtained, The process returns to step S306, and the processing from step S306 is repeated.

When a positive result is obtained in step S307, the process proceeds to step S309, the bank address value is initialized to "0" again, and then step S310.
At, the row address value is incremented by 2. Then, in the subsequent step S311, it is determined whether or not the row address value is “238” or more, and when a negative result is obtained, the process is continuously performed from step S302 to input one line. Pixel data write processing is performed.

On the other hand, if a positive result is obtained in step S311, the flow advances to step S312 to initialize the row address value (if the row address value is "238", "0").
And if the row address value is "239", the column address value is initialized to "1". Then, in step S313, it is determined whether the column address value is "0". If a negative result is obtained in step S313, the column address value is decremented by 1 in step S314, and then the process proceeds to step S316. On the other hand, if a positive result is obtained in step S313, the row address value is initialized to "255" in step S315, and then the process proceeds to step S316. Then, in step S316, it is determined whether or not the writing processing of the input pixel data of 480 lines, that is, the input image data of one frame is completed. If not completed, the processing is performed from step S302, and at the time of the completion. The writing process is completed.

FIG. 15 is a flow chart showing the processing operation executed by the memory controller 2 in order to perform the reading operation according to the second image conversion example described above. Also in the following processing, the output timing of various commands output from the memory controller 2 to the image memory 3 is the timing corresponding to the clock CLK shown in FIG.

In this case, the memory controller 2 initializes the bank address value to "0", the row address value to "0", and the column address value to "0" in step S401. Then, in the next step S402, the active command, the bank address, and the row address are output, and in the subsequent step S403, the read command, the bank address, and the column address are output.

Next, the memory controller 2 increments the column address value by 1 in step S404, and then determines in step S405 whether or not the column address value is "256". Here, when a negative result is obtained in step S405, the process returns to step S403 and the process is repeated from step S403.

When a positive result is obtained in step S405, the process proceeds to step S406, the column address value is initialized to "0", and the following step S40 is performed.
At 7, the precharge command is output. Then, in the subsequent step S408, the row address value is incremented by 1. And the next step S
After outputting the active command, the bank address, and the row address again in 409, and in the subsequent step S410, the read command, the bank address, and the column address are output. Then continue, step S4
After incrementing the column address value by 1 in 11, the column address value is set to "22" in step S412.
It is determined whether it is "4".

Here, when a negative result is obtained, the process returns to step S410, and the processing from step S410 is repeated to read the data from the memory area corresponding to the row address. And step S
When a positive result is obtained in 412, step S4
In step S13, the column address value is initialized to "0" again, and after the precharge command is output in step S414, the bank address value is incremented by 1 in step S415.
In other words, the output image data for one line is read by performing the processing from step S402 to step S414.

Then, in the next step S416,
It is determined whether the bank address value is "4", and if the bank address value is not "4", step S
In step 418, the row address value is decremented by 1, and the process proceeds to step S419. Then, in step S419, it is determined whether or not the input image data for one frame has been read from the image memory 3, and if a negative result is obtained, the processing is performed from step S402. If it is determined in step S416 that the bank address value is "4", the process proceeds to step S417.
The bank address value is initialized to the initial value "0", the row address value is incremented by 1, and the process proceeds to step S419. Then, when a positive result is obtained in step S419, the process may be ended assuming that the reading of the output image data for one frame is completed.

Note that the write operation procedure and the read procedure executed for the image memory 3 for the image conversion described above are merely examples, and the image conversion method of the present invention uses the write operation procedure and the read operation procedure described above. The reading procedure is not limited. That is, according to the image conversion method of the present invention, every time one line (or one pixel) of image data is written in the image memory 3, the bank is switched and one pixel (from the image memory 3) is changed. It goes without saying that a writing operation procedure or a reading procedure for the image memory 3 may be performed such that the bank is switched every time the image data of one line) is read.

Further, in the image conversion examples described so far, the case where the input image is rotated by 90 ° in the clockwise direction and displayed is described as an example, but this is merely an example, and according to the present invention, the input image is converted. Is displayed by rotating it counterclockwise by 90 °, or an inverted image obtained by inverting the input image is displayed.
Of course, it is also possible to display the image by rotating it by 0 °.

Further, the deflection scanning of a normal image display device is
Although horizontal deflection scanning is performed, an image display device of vertical deflection scanning can be realized by performing image conversion processing for rotating input image data by 90 ° according to the present invention.
That is, by performing the image conversion process of rotating the input image data by 90 ° according to the present invention, the input image can be displayed as the display image in the proper orientation on the vertical deflection scanning image display device.

[0089]

As described above, according to the present invention, the image conversion processing of the input image data can be performed by a faster access operation than the conventional random access operation. Even if is configured by a large-capacity and low-priced dynamic random access memory, the image conversion processing of the input image can be performed in real time. Further, if the storage means is constituted by a dynamic random access memory, there is an advantage that the storage means can be operated with low power consumption. In particular, the present invention is suitable for image conversion of moving images because it can perform image conversion processing of an input image in real time.

Therefore, when the present invention as described above is applied to various image display devices, for example, the screen orientation of the image display device is changed to 9
It is possible to use it in an unprecedented form, such as using it in a state of being rotated 0 °.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image conversion apparatus and its peripheral circuits according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a bank configuration of an image memory.

FIG. 3 is a diagram showing a relationship between input image data and output image data when an input image is rotated by 90 ° and displayed.

FIG. 4 is a diagram illustrating a procedure for writing image data in the first image conversion example.

FIG. 5 is a diagram illustrating a procedure of reading image data in the first image conversion example.

FIG. 6 is a diagram showing a write timing of image data in the first image conversion example.

FIG. 7 is a diagram showing a read timing of image data in the first image conversion example.

FIG. 8 is a flowchart showing a processing operation for realizing a writing process of image data in the first image conversion example.

FIG. 9 is a flowchart showing a processing operation for realizing image data read processing in the first image conversion example.

FIG. 10 is a diagram illustrating a procedure for writing image data in the second image conversion example.

FIG. 11 is a diagram illustrating a procedure of reading image data in the second image conversion example.

FIG. 12 is a diagram showing a write timing of image data in the second image conversion example.

FIG. 13 is a diagram showing a read timing of image data in the second image conversion example.

FIG. 14 is a flowchart showing a processing operation for realizing a writing process of image data in the second image conversion example.

FIG. 15 is a flowchart showing a processing operation for realizing image data read processing in the second image conversion example.

[Explanation of symbols]

1 A / D converter, 2 memory controller, 3
Memory, D / A converter, 5 matrix circuits, 6
CRT, 7 synchronization signal generator, 8 deflection circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 6, 2001 (2001.8.6)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

The image memory 3 is, for example, a large capacity SDRA.
M (Synchronous Dynamic Random Access Memory) or DDR SDRAM (Double Data Rate Synchrono)
us Dynamic Random Access Memory) , FCRAM (Fas
t Cycle Random Access Memory), and the inside thereof has a so-called bank structure divided into a plurality of data storage areas.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

At this time, the input image data for one line is input to each of the banks A to D from the head position in the column direction (col).
Write in the (umn direction). However, in this case, since only 256 pixels of data can be written in the column direction of each bank A to D, one line of input image data is stored in the memory of two rows (Row) of each bank A to D. I am trying to write using the area. in this case,
Pixel data for 256 pixels is written in the row with the lower address, and pixel data for the remaining 224 pixels is written in the row with the higher address. In this case, in the upper column, 32 pixels (256 pixels−224 pixels = 32)
Although the memory area of (pixels) is left, data is not written in the memory area.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

The address value x of each bank A, B, C, D in the column direction (column direction) is set to "0 to 255".
And the address value y in the row direction (row direction) of the banks A, B, C, D is set to "0 to 2047". Then, based on these column address values x, the column addresses output from the memory controller 2 to the image memory 3 are respectively set to "Co
l Ax "," Col Bx "," Col Cx "," C
ol Dx ”, and the row addresses output from the memory controller 2 to the image memory 3 based on the row address value y are“ RowAy ”,“ Row By ”,
Notated as “Row Cy” and “Row Dy”.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0078

[Correction method] Change

[Correction content]

When a positive result is obtained in step S307, the process proceeds to step S309, the bank address value is initialized to "0" again, and then step S310.
At, the row address value is incremented by 2. Then, in the subsequent step S311, it is determined whether or not the row address value is “ 240 ” or more, and when a negative result is obtained, the processing is continuously performed from step S302 to input one line. Pixel data write processing is performed.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0079

[Correction method] Change

[Correction content]

On the other hand, if a positive result is obtained in step S311, the flow advances to step S312 to initialize the row address value ("0" if the row address value is " 240 ").
And if the row address value is " 241 ", the column address value is initialized to "1". Then, in step S313, it is determined whether the column address value is "0". If a negative result is obtained in step S313, the column address value is decremented by 1 in step S314, and then the process proceeds to step S316. On the other hand, if a positive result is obtained in step S313, the row address value is initialized to "255" in step S315, and then the process proceeds to step S316. Then, in step S316, it is determined whether or not the writing processing of the input pixel data of 480 lines, that is, the input image data of one frame is completed. If not completed, the processing is performed from step S302, The writing process is completed.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/14 G09G 5/36 530F 5/262 520K F term (reference) 5B047 CA21 CB25 EA02 EB11 5C021 PA71 PA82 PA83 YC03 YC04 ZA03 5C023 AA01 AA03 CA01 DA01 DA03 DA04 5C082 AA01 AA02 BA02 BA12 BB15 BB53 CA42 DA54 DA55 DA73 DA76 DA86 DA89 EA08 MM06 MM07

Claims (6)

[Claims] 1. As an image conversion method for converting an input image into a predetermined output image, when writing input image data into a storage means having a plurality of data storage areas, one line of data is stored in the data storage area. Each time the input image data is written by the burst write operation, the data storage areas are sequentially switched, and during the switching of the data storage areas, the same write address is designated between the data storage areas. Procedure and when reading output image data from the data storage area, the data storage area is sequentially switched every time one pixel of image data is read from the data storage area, and the data storage area is switched. The same read address can be specified between the data storage areas during one cycle. Image conversion method characterized by performing on the read procedure is a. 2. An image conversion apparatus for converting an input image into a predetermined output image, and a storage means having a plurality of data storage areas, and when writing input image data, one line is stored in the data storage area. Each time the input image data of is written by the burst write operation, the data storage area is switched, and during the switching of the data storage area, the same write address is designated between the data storage areas. And when the output image data is read from the data storage area, the data storage area is switched and the data storage area is switched each time the image data for one pixel is read from the data storage area. The same read address should be specified between data storage areas during one cycle. An image conversion apparatus comprising: 3. The image conversion apparatus according to claim 2, wherein the storage means is a dynamic random access memory having a plurality of data storage areas. 4. As an image conversion method for converting an input image into a predetermined output image, when writing the input image data to a storage means having a plurality of data storage areas, the input image data is stored in the data storage area.
Each time the input image data for a pixel is written, the data storage area is switched, and during the switching of the data storage area, the same write address is designated between the data storage areas. When the output image data is read from the data storage area, each time the output image data for one line is read from the data storage area by the burst read operation, the data storage area is switched and the data storage area is also changed. An image conversion method characterized by executing a read procedure in which the same read address is designated between the data storage areas during one cycle of switching of, and. 5. An image conversion device for converting an input image into a predetermined output image, and a storage means having a plurality of data storage areas, and when writing input image data, one pixel is stored in the data storage area. Each time you write the input image data of
While switching the data storage areas, while the switching of the data storage areas completes one cycle, writing means for designating the same write address between the data storage areas and reading of output image data from the data storage areas In this case, each time the output image data for one line is read from the data storage area by the burst read operation, the data storage area is switched, and the data storage area is stored while the switching of the data storage area is complete. An image conversion apparatus comprising: a reading unit configured to specify the same reading address between areas. 6. The image conversion apparatus according to claim 5, wherein the storage means is a dynamic random access memory having a plurality of data storage areas.