JP2003100552A - Three-terminal ceramic capacitor - Google Patents
Three-terminal ceramic capacitorInfo
- Publication number
- JP2003100552A JP2003100552A JP2001287251A JP2001287251A JP2003100552A JP 2003100552 A JP2003100552 A JP 2003100552A JP 2001287251 A JP2001287251 A JP 2001287251A JP 2001287251 A JP2001287251 A JP 2001287251A JP 2003100552 A JP2003100552 A JP 2003100552A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- external
- electrode
- internal
- ground electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 18
- 239000000919 ceramic Substances 0.000 claims abstract description 31
- 239000003990 capacitor Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 238000003780 insertion Methods 0.000 description 5
- 238000003475 lamination Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子機器の高周波
ノイズを除去するために使用される３端子構造を持つ積
層セラミックコンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic capacitor having a three-terminal structure used for removing high frequency noise of electronic equipment.
【０００２】[0002]
【従来の技術】３端子型コンデンサは、２端子型コンデ
ンサと比較して等価直列インダクタンスを小さくできる
ため、例えば電源ラインからの高周波ノイズをバイパス
経路を設けて除去するバイパスコンデンサとして用いた
場合において、高周波帯域における挿入損失特性の劣化
を少なくすることができる。従来の３端子型セラミック
コンデンサにおいては、例えば図２に示すような以下の
構成のものが知られている。図２において（Ａ）は斜視
図で、（Ｂ）、（Ｃ）は積層前のセラミック素体の構成
の１例を示す図である。セラミック素体４０が積層され
た複数の誘電体層を有しており、これらの誘電体層の片
面に内部信号電極４６及び内部グランド電極５０が交互
にプリントされ、内部信号電極４６と内部グランド電極
５０が誘電体層を挟むことで容量性素子を形成してい
る。セラミック素体４０の長さ方向に垂直な第１の外面
５６−１、５６−２に、信号または電源のラインが接続
される外部信号電極４２−１、４２−２がそれぞれプリ
ントされ、外部信号電極４２−１、４２−２はそれぞれ
第１の外面５６−１、５６−２を覆っている。一方、セ
ラミック素体４０の幅方向に垂直な第２の外面５８−
１、５８−２に、接地される外部グランド電極４４−
１、４４−２がそれぞれプリントされている。内部信号
電極４６は、第１の外面５６−１、５６−２の両方の位
置で外部信号電極４２−１、４２−２と電気的に接続さ
れている。一方、内部グランド電極５０は、第２の外面
５８−１、５８−２の両方の位置で外部グランド電極４
４−１、４４−２と電気的に接続されている。図２
（Ｂ）においては、内部信号電極４６の幅方向の寸法が
長さ方向に関して一定であり、内部グランド電極５０の
長さ方向の寸法が幅方向に関して一定である。一方、図
２（Ｃ）においては、内部信号電極４６の幅方向の寸法
が長さ方向に関して一定であるが、内部グランド電極５
０については長さ方向の寸法を途中で大きくし十字状の
電極形状とすることで、内部信号電極４６と内部グラン
ド電極５０との対向面積を大きくし、コンデンサ容量を
大きくしている。2. Description of the Related Art A three-terminal type capacitor can reduce the equivalent series inductance as compared with a two-terminal type capacitor. Therefore, for example, when it is used as a bypass capacitor for removing high frequency noise from a power line by providing a bypass path, It is possible to reduce the deterioration of the insertion loss characteristic in the high frequency band. As a conventional three-terminal type ceramic capacitor, for example, one having the following configuration as shown in FIG. 2 is known. In FIG. 2, (A) is a perspective view, and (B) and (C) are diagrams showing an example of the configuration of the ceramic body before lamination. The ceramic element body 40 has a plurality of laminated dielectric layers, and the internal signal electrodes 46 and the internal ground electrodes 50 are alternately printed on one surface of these dielectric layers to form the internal signal electrodes 46 and the internal ground electrodes. 50 sandwiches the dielectric layer to form a capacitive element. External signal electrodes 42-1 and 42-2, to which a signal or power supply line is connected, are printed on the first outer surfaces 56-1 and 56-2 perpendicular to the length direction of the ceramic body 40, respectively. The electrodes 42-1 and 42-2 cover the first outer surfaces 56-1 and 56-2, respectively. On the other hand, the second outer surface 58- which is perpendicular to the width direction of the ceramic body 40-
The external ground electrode 44- grounded to 1, 58-2
1, 44-2 are printed respectively. The internal signal electrode 46 is electrically connected to the external signal electrodes 42-1 and 42-2 at both positions of the first outer surfaces 56-1 and 56-2. On the other hand, the internal ground electrode 50 has the external ground electrode 4 at both positions of the second outer surfaces 58-1 and 58-2.
It is electrically connected to 4-1 and 44-2. Figure 2
In (B), the widthwise dimension of the internal signal electrode 46 is constant in the lengthwise direction, and the lengthwise dimension of the internal ground electrode 50 is constant in the widthwise direction. On the other hand, in FIG. 2C, the size of the internal signal electrode 46 in the width direction is constant in the length direction.
For 0, the dimension in the lengthwise direction is enlarged in the middle to form a cross-shaped electrode shape, thereby increasing the facing area between the internal signal electrode 46 and the internal ground electrode 50 and increasing the capacitance of the capacitor.
【０００３】[0003]
【発明が解決しようとする課題】近年、除去対象となる
ノイズが高周波化しており、３端子のコンデンサにおい
ても高周波帯域における挿入損失特性の劣化を防ぐため
に等価直列インダクタンスをさらに小さくする必要があ
る。また、周波数及び強さが様々なノイズに対応するた
めには、コンデンサ容量を任意に設定できる必要がある
ので、大きいコンデンサ容量を確保できることが必要と
なる。しかしながら、図２（Ｂ）における従来のセラミ
ックコンデンサにおいては、内部信号電極４６と内部グ
ランド電極５０との対向部分と外部グランド電極４４−
１、４４−２との距離が比較的短いため、等価直列イン
ダクタンスは大きくないものの、内部信号電極４６と内
部グランド電極５０との対向面積が小さく、大きいコン
デンサ容量を確保できないので、コンデンサ容量を任意
に設定できない。一方、図２（Ｃ）における従来のセラ
ミックコンデンサにおいては、内部信号電極４６と内部
グランド電極５０との対向面積が大きくとれるため、大
きいコンデンサ容量を確保できるが、内部信号電極４６
と内部グランド電極５０との対向部分と外部グランド電
極４４−１、４４−２との距離が長い部分が存在するた
め、等価直列インダクタンスは大きくなる。このように
従来の３端子構造を持つセラミックコンデンサにおいて
は、等価直列インダクタンスを小さくし、かつコンデン
サ容量を任意に設定することができないという課題があ
った。In recent years, the noise to be removed has become higher in frequency, and it is necessary to further reduce the equivalent series inductance of a three-terminal capacitor in order to prevent deterioration of insertion loss characteristics in the high frequency band. Further, in order to cope with noise of various frequencies and intensities, it is necessary to arbitrarily set the capacitor capacity, so it is necessary to ensure a large capacitor capacity. However, in the conventional ceramic capacitor shown in FIG. 2B, the opposing portion of the internal signal electrode 46 and the internal ground electrode 50 and the external ground electrode 44-
Although the equivalent series inductance is not large because the distance to 1, 44-2 is relatively short, the facing area between the internal signal electrode 46 and the internal ground electrode 50 is small, and a large capacitor capacity cannot be secured. Cannot be set to. On the other hand, in the conventional ceramic capacitor shown in FIG. 2 (C), since the facing area between the internal signal electrode 46 and the internal ground electrode 50 can be made large, a large capacitor capacitance can be secured, but the internal signal electrode 46 can be secured.
Since there is a portion where the distance between the external ground electrodes 44-1 and 44-2 and the internal ground electrode 50 facing each other is long, the equivalent series inductance increases. As described above, the conventional ceramic capacitor having a three-terminal structure has a problem that the equivalent series inductance cannot be reduced and the capacitor capacitance cannot be set arbitrarily.
【０００４】本発明は上記課題に鑑みてなされたもので
あり、等価直列インダクタンスを小さくし、かつコンデ
ンサ容量を任意に設定することができる３端子型セラミ
ックコンデンサを提供することを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a three-terminal type ceramic capacitor capable of reducing the equivalent series inductance and arbitrarily setting the capacitance of the capacitor.
【０００５】[0005]
【課題を解決するための手段】このような目的を達成す
るために、本発明に係る３端子型セラミックコンデンサ
は、積層された複数の誘電体層と、該誘電体層間に交互
に設けられた内部信号電極及び内部グランド電極と、を
有するセラミック素体と、前記セラミック素体に長さ方
向Ｘ、幅方向Ｙ及び厚み方向Ｚを仮想した場合に、前記
セラミック素体のＸ方向に垂直な第１の外面の両方に設
けられた外部信号電極と、前記セラミック素体のＹ方向
に垂直な第２の外面の両方に設けられ、該第２の外面の
両方を覆う外部グランド電極と、を備え、前記内部信号
電極は、前記第１の外面の両方の位置で前記外部信号電
極と電気的に接続され、前記内部グランド電極は、前記
第２の外面の両方におけるＸ方向のすべての位置で前記
外部グランド電極と電気的に接続され、かつ前記誘電体
層の周囲における前記外部信号電極と接する部分を除い
て前記誘電体層間に設けられ、前記セラミック素体のＸ
方向長さがＹ方向長さより長いことを特徴とする。In order to achieve such an object, the three-terminal type ceramic capacitor according to the present invention is provided with a plurality of laminated dielectric layers and alternately provided between the dielectric layers. When a length direction X, a width direction Y, and a thickness direction Z are hypothesized on the ceramic body having an internal signal electrode and an internal ground electrode, a first perpendicular to the X direction of the ceramic body is assumed. An external signal electrode provided on both of the outer surfaces of the first and the second outer surface of the ceramic element body perpendicular to the Y direction, and an external ground electrode covering both of the second outer surfaces. , The internal signal electrode is electrically connected to the external signal electrode at both positions on the first outer surface, and the internal ground electrode is at all positions in the X direction on both the second outer surface. External ground electrode It is electrically connected, and provided on the external signal electrodes and the contact portions except for the dielectric layers in the periphery of the dielectric layer, X of the ceramic body
The directional length is longer than the Y-direction length.
【０００６】このように、セラミック素体の第２の外面
の両方を外部グランド電極で覆い、内部グランド電極
は、第２の外面の両方におけるＸ方向のすべての位置で
外部グランド電極と電気的に接続され、かつ誘電体層の
周囲における外部信号電極と接する部分を除いて誘電体
層間に設けられることにより、容量性素子を形成する内
部信号電極と内部グランド電極との対向部分と外部グラ
ンド電極との間の信号線路について、線路幅（Ｘ方向の
長さ）を広くし、かつ距離を短くできるので、等価イン
ダクタンスを小さくすることができる。そして、セラミ
ック素体のＸ方向長さをＹ方向長さより長く設定するこ
とによっても、上記の対向部分と外部グランド電極との
間の信号線路について、線路幅（Ｘ方向の長さ）を広く
し、かつ距離を短くすることができるので、等価インダ
クタンスをさらに小さくすることができる。したがっ
て、高周波帯域における挿入損失特性の劣化を防ぐこと
ができる。また、コンデンサ容量を任意に設定すること
で、周波数及び強さが様々なノイズに対応することがで
きる。Thus, both the second outer surface of the ceramic body is covered with the external ground electrode, and the internal ground electrode is electrically connected to the external ground electrode at all positions in the X direction on both the second outer surface. By being provided between the dielectric layers except for the portion that is connected and is in contact with the external signal electrode around the dielectric layer, the opposing portion of the internal signal electrode and the internal ground electrode forming the capacitive element and the external ground electrode Since the line width (length in the X direction) can be widened and the distance can be shortened for the signal line between the two, the equivalent inductance can be reduced. The line width (length in the X direction) of the signal line between the facing portion and the external ground electrode can be increased by setting the length in the X direction of the ceramic body longer than the length in the Y direction. Since the distance can be shortened, the equivalent inductance can be further reduced. Therefore, it is possible to prevent the deterioration of the insertion loss characteristic in the high frequency band. Further, by arbitrarily setting the capacitor capacity, it is possible to deal with noises having various frequencies and strengths.
【０００７】本発明に係る３端子型セラミックコンデン
サは、さらに、前記内部信号電極は、前記誘電体層の周
囲における前記外部グランド電極と接する部分を除いて
前記誘電体層間に設けられることを特徴とする。The three-terminal ceramic capacitor according to the present invention is further characterized in that the internal signal electrode is provided between the dielectric layers except a portion around the dielectric layer, which is in contact with the external ground electrode. To do.
【０００８】このように、内部信号電極は、誘電体層の
周囲における外部グランド電極と接する部分を除いて誘
電体層間に設けられることにより、内部信号電極と内部
グランド電極との対向面積を大きくすることができるの
で、等価直列インダクタンスを小さくした状態で、大き
いコンデンサ容量を確保することができる。As described above, the internal signal electrode is provided between the dielectric layers except for the portion in contact with the external ground electrode around the dielectric layer, thereby increasing the facing area between the internal signal electrode and the internal ground electrode. Therefore, it is possible to secure a large capacitor capacity while reducing the equivalent series inductance.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施の形態（以下
実施形態という）を、図面に従って説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.
【００１０】図１は、本発明の実施形態に係る３端子型
セラミックコンデンサの構成を示す図であり、（Ａ）は
斜視図で、（Ｂ）は積層前のセラミック素体の構成を示
す図である。３端子型セラミックコンデンサは、後述す
る構成のセラミック素体１０、外部信号電極１２−１、
１２−２及び外部グランド電極１４−１、１４−２によ
り構成されている。FIG. 1 is a diagram showing a structure of a three-terminal type ceramic capacitor according to an embodiment of the present invention, (A) is a perspective view, and (B) is a diagram showing a structure of a ceramic body before lamination. Is. The three-terminal type ceramic capacitor includes a ceramic element body 10, an external signal electrode 12-1, and
12-2 and the external ground electrodes 14-1 and 14-2.
【００１１】セラミック素体１０は、片面に内部信号電
極１６がプリントされている第１の誘電体層１８と片面
に内部グランド電極２０がプリントされている第２の誘
電体層２２とが交互に任意の枚数積層されており、その
上下には電極がプリントされていない第３の誘電体層２
４が積層されている。このように、内部信号電極１６と
内部グランド電極２０とが誘電体層を挟むことで容量性
素子を形成している。In the ceramic body 10, a first dielectric layer 18 having an internal signal electrode 16 printed on one surface and a second dielectric layer 22 having an internal ground electrode 20 printed on one surface alternate with each other. Third dielectric layer 2 in which any number of layers are laminated and electrodes are not printed above and below it
4 are stacked. In this way, the internal signal electrode 16 and the internal ground electrode 20 sandwich the dielectric layer to form a capacitive element.
【００１２】ここで、図１（Ａ）に示すようにセラミッ
ク素体１０の長さ方向をＸ方向、幅方向をＹ方向及び厚
み方向をＺ方向とする座標軸を規定する。セラミック素
体１０のＸ方向に垂直な第１の外面２６−１、２６−２
には、信号または電源のラインが接続される外部信号電
極１２−１、１２−２がそれぞれプリントされている。
一方、セラミック素体１０のＹ方向に垂直な第２の外面
２８−１、２８−２には、接地される外部グランド電極
１４−１、１４−２がそれぞれプリントされており、外
部グランド電極１４−１、１４−２はそれぞれ第２の外
面２８−１、２８−２を覆っている。なお、図１（Ａ）
に示すように、外部信号電極１２−１、１２−２は、セ
ラミック素体１０への取り付けや基板への実装のために
セラミック素体１０の上下面に所定の長さ延長されてい
る。同様に外部グランド電極１４−１、１４−２につい
ても、セラミック素体１０の上下面及び第１の外面２６
−１、２６−２に所定の長さ延長されている。Here, as shown in FIG. 1A, coordinate axes having the length direction of the ceramic body 10 as the X direction, the width direction as the Y direction, and the thickness direction as the Z direction are defined. First outer surfaces 26-1 and 26-2 perpendicular to the X direction of the ceramic body 10.
External signal electrodes 12-1 and 12-2, to which a signal or power line is connected, are printed on the printed circuit board.
On the other hand, external ground electrodes 14-1 and 14-2 to be grounded are printed on the second outer surfaces 28-1 and 28-2 of the ceramic body 10 which are perpendicular to the Y direction. -1, 14-2 cover the second outer surfaces 28-1, 28-2, respectively. Note that FIG. 1 (A)
As shown in FIG. 3, the external signal electrodes 12-1 and 12-2 are extended by a predetermined length on the upper and lower surfaces of the ceramic body 10 for attachment to the ceramic body 10 and mounting on the substrate. Similarly, for the external ground electrodes 14-1 and 14-2 as well, the upper and lower surfaces of the ceramic body 10 and the first outer surface 26.
-1, 26-2 is extended by a predetermined length.
【００１３】内部信号電極１６は、第１の誘電体層１８
の周囲における外部信号電極１２−１、１２−２と接す
るすべての部分で外部信号電極１２−１、１２−２の両
方と電気的に接続されており、かつ第１の誘電体層１８
の周囲における外部グランド電極１４−１、１４−２と
接する部分を除いて第１の誘電体層１８の片面にプリン
トされている。一方、内部グランド電極２０は、第２の
誘電体層２２の周囲における外部グランド電極１４−
１、１４−２と接するすべての部分で外部グランド電極
１４−１、１４−２と電気的に接続されており、かつ第
２の誘電体層２２の周囲における外部信号電極１２−
１、１２−２と接する部分を除いて第２の誘電体層２２
の片面にプリントされている。また、セラミック素体１
０のＸ方向長さはＹ方向長さより長く設定されている。The internal signal electrode 16 is a first dielectric layer 18
Is electrically connected to both the external signal electrodes 12-1 and 12-2 at all portions in contact with the external signal electrodes 12-1 and 12-2 around the first dielectric layer 18 and
Is printed on one surface of the first dielectric layer 18 except for the portion in the vicinity of which the external ground electrodes 14-1 and 14-2 are in contact. On the other hand, the internal ground electrode 20 is the external ground electrode 14- around the second dielectric layer 22.
1 and 14-2 are electrically connected to the external ground electrodes 14-1 and 14-2 at all portions in contact with the external signal electrodes 12- around the second dielectric layer 22.
The second dielectric layer 22 except for the portions in contact with 1 and 12-2
It is printed on one side of. Also, the ceramic body 1
The length of 0 in the X direction is set to be longer than the length in the Y direction.
【００１４】本実施形態においては、外部グランド電極
１４−１、１４−２はそれぞれ第２の外面２８−１、２
８−２を覆う。そして、内部グランド電極２０が、第２
の誘電体層２２の周囲における外部グランド電極１４−
１、１４−２と接するすべての部分で外部グランド電極
１４−１、１４−２と電気的に接続されており、かつ第
２の誘電体層２２の周囲における外部信号電極１２−
１、１２−２と接する部分を除いて第２の誘電体層２２
の片面にプリントされる。したがって、容量性素子を形
成する内部信号電極１６と内部グランド電極２０との対
向部分と外部グランド電極１４−１、１４−２との間の
信号線路について、線路幅（Ｘ方向の長さ）を広くし、
かつ距離を短くすることができるので、等価インダクタ
ンスを小さくすることができる。そして、セラミック素
体１０のＸ方向長さをＹ方向長さより長く設定すること
によっても、上記の対向部分と外部グランド電極１４−
１、１４−２との間の信号線路について、線路幅（Ｘ方
向の長さ）を広くし、かつ距離を短くすることができる
ので、等価インダクタンスをさらに小さくすることがで
きる。したがって、高周波帯域における挿入損失特性の
劣化を防ぐことができる。In the present embodiment, the external ground electrodes 14-1 and 14-2 are the second outer surfaces 28-1 and 2-2, respectively.
Cover 8-2. Then, the internal ground electrode 20 is
External ground electrode 14-around the dielectric layer 22 of
1 and 14-2 are electrically connected to the external ground electrodes 14-1 and 14-2 at all portions in contact with the external signal electrodes 12- around the second dielectric layer 22.
The second dielectric layer 22 except for the portions in contact with 1 and 12-2
Is printed on one side. Therefore, the line width (length in the X direction) of the signal line between the opposing portions of the internal signal electrode 16 and the internal ground electrode 20 forming the capacitive element and the external ground electrodes 14-1 and 14-2 is determined. Widen and
Moreover, since the distance can be shortened, the equivalent inductance can be reduced. Also, by setting the length of the ceramic body 10 in the X direction to be longer than the length in the Y direction, the opposing portion and the external ground electrode 14-
Since the line width (length in the X direction) of the signal line between the signal lines 1 and 14-2 can be widened and the distance can be shortened, the equivalent inductance can be further reduced. Therefore, it is possible to prevent the deterioration of the insertion loss characteristic in the high frequency band.
【００１５】また、内部信号電極１６が、第１の誘電体
層１８の周囲における外部グランド電極１４−１、１４
−２と接する部分を除いて第１の誘電体層１８の片面に
プリントされることにより、内部信号電極１６と内部グ
ランド電極２０との対向面積を大きくすることができる
ので、コンデンサの容量を大きく設定することができ
る。このように、大きいコンデンサ容量を確保できるの
で、コンデンサ容量を任意に設定することで、周波数及
び強さが様々なノイズに対応することができる。Further, the internal signal electrode 16 is the external ground electrodes 14-1 and 14 around the first dielectric layer 18.
-2 is printed on one surface of the first dielectric layer 18 except for the portion in contact with -2, so that the facing area between the internal signal electrode 16 and the internal ground electrode 20 can be increased, so that the capacitance of the capacitor can be increased. Can be set. In this way, since a large capacitor capacity can be secured, it is possible to cope with noise of various frequencies and strengths by setting the capacitor capacity arbitrarily.
【００１６】なお、本実施形態においては、内部信号電
極１６が、第１の誘電体層１８の周囲における外部グラ
ンド電極１４−１、１４−２と接する部分を除いて第１
の誘電体層１８の片面にプリントされている構成につい
て説明したが、本実施形態はこのような構成に限るもの
ではなく、除去対象とするノイズの強さ及び周波数に応
じて内部信号電極１６の形状を任意に変更して内部信号
電極１６と内部グランド電極２０との対向面積を任意に
設定することで、コンデンサ容量を任意に設定してよ
い。In this embodiment, the internal signal electrode 16 is the first dielectric layer 18 except the portion in contact with the external ground electrodes 14-1 and 14-2.
Although the structure printed on one surface of the dielectric layer 18 has been described, the present embodiment is not limited to such a structure, and the internal signal electrode 16 of the internal signal electrode 16 may be formed according to the intensity and frequency of noise to be removed. The capacitor capacitance may be arbitrarily set by arbitrarily changing the shape and arbitrarily setting the facing area between the internal signal electrode 16 and the internal ground electrode 20.
【００１７】[0017]
【発明の効果】以上説明したように、本発明において
は、セラミック素体の第２の外面の両方を外部グランド
電極で覆い、内部グランド電極は、第２の外面の両方に
おける長さ方向のすべての位置で外部グランド電極と電
気的に接続され、かつ誘電体層の周囲における外部信号
電極と接する部分を除いて誘電体層間に設けられること
により、等価インダクタンスを小さくすることができ、
高周波帯域における挿入損失特性の劣化を防ぐことがで
きる。そして、コンデンサ容量を任意に設定することが
でき、様々なノイズに対応することができる。As described above, according to the present invention, both the second outer surface of the ceramic body is covered with the outer ground electrode, and the inner ground electrode is provided on both the second outer surface in the longitudinal direction. It is possible to reduce the equivalent inductance by being electrically connected to the external ground electrode at the position of, and provided between the dielectric layers except for the portion in contact with the external signal electrode around the dielectric layer,
It is possible to prevent deterioration of insertion loss characteristics in a high frequency band. Then, the capacitor capacity can be arbitrarily set, and various noises can be dealt with.
【図１】 本発明の実施形態に係る３端子型セラミック
コンデンサの構成を示す図で、（Ａ）は斜視図で、
（Ｂ）は積層前のセラミック素体の構成を示す図であ
る。FIG. 1 is a diagram showing a configuration of a three-terminal type ceramic capacitor according to an embodiment of the present invention, in which (A) is a perspective view,
(B) is a diagram showing a configuration of a ceramic body before lamination.
【図２】 従来の３端子型セラミックコンデンサの構成
を示す図で、（Ａ）は斜視図で、（Ｂ）、（Ｃ）は積層
前のセラミック素体の構成の１例を示す図である。FIG. 2 is a diagram showing a configuration of a conventional three-terminal type ceramic capacitor, (A) is a perspective view, and (B) and (C) are diagrams showing an example of a configuration of a ceramic body before lamination. .
１０ セラミック素体、１２−１，１２−２ 外部信号
電極、１４−１，１４−２ 外部グランド電極、１６
内部信号電極、２０ 内部グランド電極。10 ceramic body, 12-1, 12-2 external signal electrode, 14-1, 14-2 external ground electrode, 16
Internal signal electrode, 20 internal ground electrode.
Claims (2)
層間に交互に設けられた内部信号電極及び内部グランド
電極と、を有するセラミック素体と、 前記セラミック素体に長さ方向Ｘ、幅方向Ｙ及び厚み方
向Ｚを仮想した場合に、前記セラミック素体のＸ方向に
垂直な第１の外面の両方に設けられた外部信号電極と、 前記セラミック素体のＹ方向に垂直な第２の外面の両方
に設けられ、該第２の外面の両方を覆う外部グランド電
極と、 を備え、 前記内部信号電極は、前記第１の外面の両方の位置で前
記外部信号電極と電気的に接続され、 前記内部グランド電極は、前記第２の外面の両方におけ
るＸ方向のすべての位置で前記外部グランド電極と電気
的に接続され、かつ前記誘電体層の周囲における前記外
部信号電極と接する部分を除いて前記誘電体層間に設け
られ、 前記セラミック素体のＸ方向長さがＹ方向長さより長い
ことを特徴とする３端子型セラミックコンデンサ。1. A ceramic body having a plurality of laminated dielectric layers, and internal signal electrodes and internal ground electrodes alternately provided between the dielectric layers, and a longitudinal direction X in the ceramic body. When the width direction Y and the thickness direction Z are hypothesized, an external signal electrode provided on both of the first outer surfaces of the ceramic element body perpendicular to the X direction, and a first signal electrode perpendicular to the Y direction of the ceramic element body. An external ground electrode that is provided on both outer surfaces of the second outer surface and covers both of the second outer surfaces, and the inner signal electrode is electrically connected to the outer signal electrode at both positions of the first outer surface. A portion where the internal ground electrode is electrically connected to the external ground electrode at all positions in the X direction on both the second outer surface and which is in contact with the external signal electrode around the dielectric layer. Excluding It provided between the dielectric layers, three-terminal ceramic capacitor X direction length of the ceramic body, characterized in that longer than the Y-direction length.
ンデンサにおいて、前記内部信号電極は、前記誘電体層
の周囲における前記外部グランド電極と接する部分を除
いて前記誘電体層間に設けられることを特徴とする３端
子型セラミックコンデンサ。2. The three-terminal ceramic capacitor according to claim 1, wherein the internal signal electrode is provided between the dielectric layers except for a portion around the dielectric layer, which is in contact with the external ground electrode. Characteristic 3-terminal type ceramic capacitor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001287251A JP4682491B2 (en) | 2001-09-20 | 2001-09-20 | 3-terminal ceramic capacitor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001287251A JP4682491B2 (en) | 2001-09-20 | 2001-09-20 | 3-terminal ceramic capacitor |
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| Publication Number | Publication Date |
|---|---|
| JP2003100552A true JP2003100552A (en) | 2003-04-04 |
| JP4682491B2 JP4682491B2 (en) | 2011-05-11 |
Family
ID=19110095
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001287251A Expired - Lifetime JP4682491B2 (en) | 2001-09-20 | 2001-09-20 | 3-terminal ceramic capacitor |
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| Country | Link |
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| JP (1) | JP4682491B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005044871A (en) * | 2003-07-24 | 2005-02-17 | Tdk Corp | Three terminal feed-through capacitor |
| US6922329B2 (en) | 2003-08-21 | 2005-07-26 | Tdk Corporation | Multilayer capacitor |
| WO2008143075A1 (en) * | 2007-05-21 | 2008-11-27 | Sanyo Electric Co., Ltd. | Electric element and its manufacturing method |
| JP2010097994A (en) * | 2008-10-14 | 2010-04-30 | Tdk Corp | Method of manufacturing laminated feedthrough capacitor |
| US8228662B2 (en) * | 2007-08-02 | 2012-07-24 | Tdk Corporation | Feedthrough capacitor with signal internal electrode layers and ground internal electrode layers alternately arranged |
| JP2013251374A (en) * | 2012-05-31 | 2013-12-12 | Tdk Corp | Multilayer capacitor |
| US10699847B2 (en) | 2016-11-23 | 2020-06-30 | Samsung Electro-Mechanics Co., Ltd. | Multilayer capacitor and board having multilayer capacitor mounted thereon |
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|---|---|---|---|---|
| JP2005044871A (en) * | 2003-07-24 | 2005-02-17 | Tdk Corp | Three terminal feed-through capacitor |
| US6922329B2 (en) | 2003-08-21 | 2005-07-26 | Tdk Corporation | Multilayer capacitor |
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| US10699847B2 (en) | 2016-11-23 | 2020-06-30 | Samsung Electro-Mechanics Co., Ltd. | Multilayer capacitor and board having multilayer capacitor mounted thereon |
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|---|---|
| JP4682491B2 (en) | 2011-05-11 |
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