JP2017107587A5 - - Google Patents

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Publication number
JP2017107587A5
JP2017107587A5 JP2017021703A JP2017021703A JP2017107587A5 JP 2017107587 A5 JP2017107587 A5 JP 2017107587A5 JP 2017021703 A JP2017021703 A JP 2017021703A JP 2017021703 A JP2017021703 A JP 2017021703A JP 2017107587 A5 JP2017107587 A5 JP 2017107587A5
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JP
Japan
Prior art keywords
operand
result
bit
significant bit
decoding
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JP2017021703A
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Japanese (ja)
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JP6373425B2 (ja
JP2017107587A (ja
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Priority claimed from US13/630,131 external-priority patent/US9122475B2/en
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JP2017021703A 2012-09-28 2017-02-08 複数のビットを左にシフトし、複数の１を複数の下位ビットにプルインするための命令 Active JP6373425B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/630,131 US9122475B2 (en) 2012-09-28 2012-09-28 Instruction for shifting bits left with pulling ones into less significant bits
US13/630,131 2012-09-28

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2015534475A Division JP6092400B2 (ja) 2012-09-28 2013-06-25 複数のビットを左にシフトし、複数の１を複数の下位ビットにプルインするための命令

Publications (3)

Publication Number Publication Date
JP2017107587A JP2017107587A (ja) 2017-06-15
JP2017107587A5 true JP2017107587A5 (2) 2018-06-21
JP6373425B2 JP6373425B2 (ja) 2018-08-15

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JP2015534475A Expired - Fee Related JP6092400B2 (ja) 2012-09-28 2013-06-25 複数のビットを左にシフトし、複数の１を複数の下位ビットにプルインするための命令
JP2017021703A Active JP6373425B2 (ja) 2012-09-28 2017-02-08 複数のビットを左にシフトし、複数の１を複数の下位ビットにプルインするための命令

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JP2015534475A Expired - Fee Related JP6092400B2 (ja) 2012-09-28 2013-06-25 複数のビットを左にシフトし、複数の１を複数の下位ビットにプルインするための命令

Country Status (7)

Country Link
US (1) US9122475B2 (2)
JP (2) JP6092400B2 (2)
KR (2) KR101817459B1 (2)
CN (1) CN104919432B (2)
DE (1) DE112013004800T5 (2)
GB (1) GB2518104B (2)
WO (1) WO2014051782A1 (2)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140189296A1 (en) * 2011-12-14 2014-07-03 Elmoustapha Ould-Ahmed-Vall System, apparatus and method for loop remainder mask instruction
CN103946795B (zh) * 2011-12-14 2018-05-15 英特尔公司 用于生成循环对齐计数或循环对齐掩码的系统、装置和方法
US9606803B2 (en) 2013-07-15 2017-03-28 Texas Instruments Incorporated Highly integrated scalable, flexible DSP megamodule architecture
US20160179548A1 (en) * 2014-12-22 2016-06-23 Intel Corporation Instruction and logic to perform an inverse centrifuge operation
EP3125108A1 (en) * 2015-07-31 2017-02-01 ARM Limited Vector processing using loops of dynamic vector length
GB2540941B (en) * 2015-07-31 2017-11-15 Advanced Risc Mach Ltd Data processing
US20180329708A1 (en) * 2015-09-19 2018-11-15 Microsoft Technology Licensing, Llc Multi-nullification
JP2018124877A (ja) * 2017-02-02 2018-08-09 富士通株式会社 コード生成装置、コード生成方法、およびコード生成プログラム
US10481910B2 (en) * 2017-09-29 2019-11-19 Intel Corporation Apparatus and method for shifting quadwords and extracting packed words
US20190196822A1 (en) * 2017-12-21 2019-06-27 Intel Corporation Apparatus and method for shifting packed quadwords and extracting packed words
US10963253B2 (en) * 2018-07-10 2021-03-30 Arm Limited Varying micro-operation composition based on estimated value of predicate value for predicated vector instruction
WO2020061139A1 (en) * 2018-09-18 2020-03-26 Optimum Semiconductor Technologies Inc. System and method to implement masked vector instructions
US11074214B2 (en) * 2019-08-05 2021-07-27 Arm Limited Data processing
US11275562B2 (en) 2020-02-19 2022-03-15 Micron Technology, Inc. Bit string accumulation
CN112492473B (zh) * 2020-11-04 2022-09-09 杭州士兰微电子股份有限公司 Mems麦克风的信号处理电路及信号处理方法
US11934327B2 (en) * 2021-12-22 2024-03-19 Microsoft Technology Licensing, Llc Systems and methods for hardware acceleration of data masking using a field programmable gate array

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0744532A (ja) * 1991-12-25 1995-02-14 Nec Corp ベクトル処理装置
US5781457A (en) * 1994-03-08 1998-07-14 Exponential Technology, Inc. Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
CN103092564B (zh) * 1995-08-31 2016-04-06 英特尔公司 执行乘加指令的处理器和对分组数据执行乘加操作的系统
US6006315A (en) * 1996-10-18 1999-12-21 Samsung Electronics Co., Ltd. Computer methods for writing a scalar value to a vector
US5832288A (en) * 1996-10-18 1998-11-03 Samsung Electronics Co., Ltd. Element-select mechanism for a vector processor
US6446198B1 (en) * 1999-09-30 2002-09-03 Apple Computer, Inc. Vectorized table lookup
JP4374363B2 (ja) * 2006-09-26 2009-12-02 Ｏｋｉセミコンダクタ株式会社 ビットフィールド操作回路
JP2010204913A (ja) * 2009-03-03 2010-09-16 Nec Computertechno Ltd ベクトル処理装置
US8009682B2 (en) * 2009-05-05 2011-08-30 Citrix Systems, Inc. Systems and methods for packet steering in a multi-core architecture
US8667042B2 (en) * 2010-09-24 2014-03-04 Intel Corporation Functional unit for vector integer multiply add instruction
WO2012137428A1 (ja) * 2011-04-08 2012-10-11 パナソニック株式会社 データ処理装置、及びデータ処理方法
US9400650B2 (en) * 2012-09-28 2016-07-26 Intel Corporation Read and write masks update instruction for vectorization of recursive computations over interdependent data
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
US9378182B2 (en) * 2012-09-28 2016-06-28 Intel Corporation Vector move instruction controlled by read and write masks
US8953785B2 (en) * 2012-09-28 2015-02-10 Intel Corporation Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor

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