JP2775845B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2775845B2 JP2775845B2 JP1116107A JP11610789A JP2775845B2 JP 2775845 B2 JP2775845 B2 JP 2775845B2 JP 1116107 A JP1116107 A JP 1116107A JP 11610789 A JP11610789 A JP 11610789A JP 2775845 B2 JP2775845 B2 JP 2775845B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- trench
- silicon
- polycrystalline silicon
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000012935 Averaging Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体素子間を分離
するための凹型溝、即ちトレンチ分離溝を有する半導体
装置の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a concave groove for separating semiconductor elements, that is, a trench isolation groove.
近年、高集積化を目的とした半導体装置では、半導体
基板に形成された素子間を絶縁分離するための分離構造
としてトレンチ分離溝が採用されている。従来、この種
のトレンチ分離溝は、半導体基板の表面から深さ方向に
狭い幅寸法の凹型溝（トレンチ）を形成し、この凹型溝
の内面に酸化膜を形成した上で、溝内に多結晶シリコン
等の材料を埋設した構成となっている。2. Description of the Related Art In recent years, in a semiconductor device for high integration, a trench isolation groove has been adopted as an isolation structure for insulating and isolating elements formed on a semiconductor substrate. Conventionally, this type of trench isolation trench has been formed by forming a concave groove (trench) having a narrow width in the depth direction from the surface of the semiconductor substrate, forming an oxide film on the inner surface of the concave groove, and forming a plurality of grooves in the groove. The structure is such that a material such as crystalline silicon is embedded.
上述した従来のトレンチ分離溝は、凹溝の内面に形成
した酸化膜は薄く、溝内は殆ど多結晶シリコンで埋設さ
れた状態にある。このため、トレンチ分離溝形成後の熱
処理工程等において、多結晶シリコンと半導体基板との
熱膨張係数の相違により半導体基板に応力が発生し、こ
の応力によって半導体基板の表面に多数の結晶欠陥が生
じて半導体装置の特性に悪影響を与えるという問題があ
る。In the above-described conventional trench isolation groove, the oxide film formed on the inner surface of the concave groove is thin, and the interior of the groove is almost buried with polycrystalline silicon. For this reason, in a heat treatment step after the trench isolation trench is formed, stress is generated in the semiconductor substrate due to a difference in thermal expansion coefficient between the polycrystalline silicon and the semiconductor substrate, and this stress causes a large number of crystal defects on the surface of the semiconductor substrate. Therefore, there is a problem that the characteristics of the semiconductor device are adversely affected.
本発明は半導体基板における結晶欠陥の発生を抑制し
た半導体装置の製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor device in which generation of crystal defects in a semiconductor substrate is suppressed.
本発明の半導体装置の製造方法は、シリコン基板の素
子分離領域にトレンチを形成する工程と、前記トレンチ
の内面に酸化膜を形成する工程と、前記トレンチ内で前
記酸化膜の上に多結晶シリコン膜と窒化膜をそれぞれ１
層以上で順次積層形成して前記トレンチを埋設する工程
とを含んでおり、前記酸化膜、多結晶シリコン膜及び窒
化膜の各膜の製造工程では、前記各膜の熱膨張係数を各
膜の膜厚比により平均化して得られる熱膨張係数が前記
シリコン基板と同程度となるように前記膜厚比を調整す
ることを特徴としている。The method of manufacturing a semiconductor device according to the present invention includes a step of forming a trench in an element isolation region of a silicon substrate, a step of forming an oxide film on an inner surface of the trench, and a step of forming polycrystalline silicon on the oxide film in the trench. 1 film and 1 nitride film
A step of burying the trenches by sequentially forming a plurality of layers, and in the step of manufacturing each of the oxide film, the polycrystalline silicon film, and the nitride film, the coefficient of thermal expansion of each of the films is determined. The film thickness ratio is adjusted so that the coefficient of thermal expansion obtained by averaging the film thickness ratio is substantially the same as that of the silicon substrate.
この製造方法では、酸化膜，多結晶シリコン膜及び窒
化膜の膜厚を調整することで、トレンチ分離溝に埋設し
た材料全体の熱膨張係数をシリコン基板に略等しくし、
トレンチ分離溝とシリコン基板との間における応力の発
生を抑制する。In this manufacturing method, by adjusting the thicknesses of the oxide film, the polycrystalline silicon film, and the nitride film, the thermal expansion coefficient of the entire material buried in the trench isolation trench is made substantially equal to that of the silicon substrate.
The generation of stress between the trench isolation groove and the silicon substrate is suppressed.
次に、本発明を図面を参照して説明する。第１図は本
発明方法で製造されるトレンチ分離溝の一実施例の縦断
面図である。シリコンからなる半導体基板１の表面に絶
縁膜２を選択形成し、この絶縁膜２をマスクにして異方
性エッチングすることにより、半導体基板１に幅２μｍ
のトレンチ３を所要深さに形成している。そして、この
トレンチ３の内側面に0.2μｍのシリコン酸化膜４を形
成する。また、トレンチ３内には0.5μｍの膜厚の多結
晶シリコン膜５を成長し、更にこの内側に0.3μｍのシ
リコン窒化膜６を成長させてトレンチ３を埋設し、トレ
ンチ分離溝を形成している。Next, the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of one embodiment of a trench isolation groove manufactured by the method of the present invention. An insulating film 2 is selectively formed on the surface of a semiconductor substrate 1 made of silicon, and anisotropically etched using the insulating film 2 as a mask, so that the semiconductor substrate 1 has a width of 2 μm.
Is formed at a required depth. Then, a 0.2 μm silicon oxide film 4 is formed on the inner side surface of the trench 3. Further, a 0.5 μm-thick polycrystalline silicon film 5 is grown in the trench 3, and a 0.3 μm silicon nitride film 6 is further grown inside the polycrystalline silicon film 5 to bury the trench 3 to form a trench isolation trench. I have.
即ち、シリコン酸化膜4,多結晶シリコン膜5,シリコン
窒化膜６のそれぞれの膜厚t4,t5,t6の比を2:5:3の比と
している。That is, the ratio of the thicknesses t 4 , t 5 , and t 6 of the silicon oxide film 4, the polycrystalline silicon film 5, and the silicon nitride film 6 is set to 2: 5: 3.
この構成により、シリコン酸化膜4,多結晶シリコン膜
5,シリコン窒化膜６のそれぞれの熱膨張係数を膜厚の厚
さ比に応じて平均化し、全体として半導体基板１を構成
するシリコンに近い熱膨張係数に調整している。したが
って、トレンチ分離溝の形成後の熱処理工程によっても
トレンチ分離溝近傍の半導体基板に生じる応力を低減
し、結晶欠陥が抑制できる。With this configuration, the silicon oxide film 4, the polycrystalline silicon film
5. The respective coefficients of thermal expansion of the silicon nitride film 6 are averaged in accordance with the thickness ratio, so that the coefficient of thermal expansion as a whole is close to the silicon constituting the semiconductor substrate 1. Therefore, even in the heat treatment step after the formation of the trench isolation trench, the stress generated in the semiconductor substrate near the trench isolation trench can be reduced, and crystal defects can be suppressed.
上述したトレンチ分離溝を本発明者が実際にシリコン
基板に構成した半導体装置に適用したところ、結晶欠陥
を従来の1/2〜1/3に軽減できた。When the inventor applied the above-described trench isolation groove to a semiconductor device actually configured on a silicon substrate, the crystal defects could be reduced to 1/2 to 1/3 of the conventional one.
第２図は本発明にかかる第２実施例の縦断面図であ
る。この実施例では、半導体基板１に幅２μｍのトレン
チ３を形成後、その内側面に0.2μｍ厚のシリコン酸化
膜４、0.3μｍ厚の多結晶シリコン膜５、0.3μｍ厚のシ
リコン窒化膜６、再度0.2μｍ厚の多結晶シリコン膜７
を順次形成し、トレンチ３を埋設してトレンチ分離溝を
形成している。FIG. 2 is a longitudinal sectional view of a second embodiment according to the present invention. In this embodiment, after a trench 3 having a width of 2 μm is formed in a semiconductor substrate 1, a silicon oxide film 4 having a thickness of 0.2 μm, a polycrystalline silicon film 5 having a thickness of 0.3 μm, a silicon nitride film 6 having a thickness of 0.3 μm, Again a 0.2 μm thick polycrystalline silicon film 7
Are sequentially formed, and the trench 3 is buried to form a trench isolation groove.
この実施例においても、少なくともシリコン酸化膜４
とシリコン窒化膜６の膜厚t4,t6の比を2:3に設定してお
り、これにより多結晶シリコン膜5,7を含むトレンチ溝
内の埋設材料の全体的な熱膨張係数をシリコンに近づ
け、応力の発生による半導体基板１の結晶欠陥の発生を
抑制することができる。Also in this embodiment, at least the silicon oxide film 4
And the thickness t 4 , t 6 of the silicon nitride film 6 are set to 2: 3, whereby the overall thermal expansion coefficient of the burying material in the trench including the polycrystalline silicon films 5, 7 is reduced. By approaching silicon, the generation of crystal defects in the semiconductor substrate 1 due to the generation of stress can be suppressed.
以上説明したように本発明は、シリコン基板に設けた
トレンチ内に酸化膜、多結晶シリコン膜、窒化膜を順次
形成してトレンチ分離溝を形成するに際し、前記各膜の
膜厚を調整し、前記各膜の熱膨張係数をその膜厚比によ
り平均化して得られる熱膨張係数をシリコン基板の熱膨
張係数に略等しくしているので、熱処理に起因するトレ
ンチ分離溝の周辺の結晶欠陥を軽減できる効果がある。As described above, the present invention adjusts the thickness of each of the films when forming an oxide film, a polycrystalline silicon film, and a nitride film sequentially in a trench provided in a silicon substrate to form a trench isolation trench, Since the coefficient of thermal expansion obtained by averaging the coefficient of thermal expansion of each film by the film thickness ratio is substantially equal to the coefficient of thermal expansion of the silicon substrate, crystal defects around the trench isolation trench due to heat treatment are reduced. There is an effect that can be done.
第１図は本発明の製造方法で製造されたトレンチ分離溝
の第１実施例の縦断面図、第２図は本発明の第２実施例
の縦断面図である。 １……半導体（シリコン）基板、２……絶縁膜、３……
トレンチ、４……シリコン酸化膜、５……多結晶シリコ
ン膜、６……シリコン窒化膜、７……多結晶シリコン
膜。FIG. 1 is a longitudinal sectional view of a first embodiment of a trench isolation groove manufactured by the manufacturing method of the present invention, and FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention. 1 ... semiconductor (silicon) substrate, 2 ... insulating film, 3 ...
Trench, 4 silicon oxide film, 5 polycrystalline silicon film, 6 silicon nitride film, 7 polycrystalline silicon film.
Claims (1)
形成する工程と、前記トレンチの内面に酸化膜を形成す
る工程と、前記トレンチ内で前記酸化膜の上に多結晶シ
リコン膜と窒化膜をそれぞれ１層以上で順次積層形成し
て前記トレンチを埋設する工程とを含み、前記酸化膜、
多結晶シリコン膜及び窒化膜の各膜の製造工程は、前記
各膜の熱膨張係数を各膜の膜厚比により平均化して得ら
れる熱膨張係数が前記シリコン基板と同程度となるよう
に前記膜厚比を調整することを特徴とする半導体装置の
製造方法。A step of forming a trench in an element isolation region of a silicon substrate, a step of forming an oxide film on an inner surface of the trench, and forming a polycrystalline silicon film and a nitride film on the oxide film in the trench. Burying the trench by sequentially laminating one or more layers.
The manufacturing process of each of the polycrystalline silicon film and the nitride film is performed so that the coefficient of thermal expansion obtained by averaging the coefficient of thermal expansion of each film by the film thickness ratio of each film is substantially the same as that of the silicon substrate. A method for manufacturing a semiconductor device, comprising adjusting a film thickness ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116107A JP2775845B2 (en) | 1989-05-11 | 1989-05-11 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116107A JP2775845B2 (en) | 1989-05-11 | 1989-05-11 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02296352A JPH02296352A (en) | 1990-12-06 |
| JP2775845B2 true JP2775845B2 (en) | 1998-07-16 |
Family
ID=14678868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1116107A Expired - Lifetime JP2775845B2 (en) | 1989-05-11 | 1989-05-11 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2775845B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100492790B1 (en) * | 1997-06-28 | 2005-08-24 | 주식회사 하이닉스반도체 | Device isolation insulating film formation method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07105436B2 (en) * | 1986-07-18 | 1995-11-13 | 株式会社東芝 | Method for manufacturing semiconductor device |
-
1989
- 1989-05-11 JP JP1116107A patent/JP2775845B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02296352A (en) | 1990-12-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5321298A (en) | Soi wafer fabrication by selective epitaxial growth | |
| JPS6052037A (en) | Manufacture of semiconductor device | |
| US5457067A (en) | Process for formation of an isolating layer for a semiconductor device | |
| US4891092A (en) | Method for making a silicon-on-insulator substrate | |
| JP2775845B2 (en) | Method for manufacturing semiconductor device | |
| JPS59186342A (en) | Manufacture of semiconductor device | |
| JPS59125638A (en) | Manufacture of semiconductor element isolation | |
| JPS618944A (en) | Semiconductor device and manufacture thereof | |
| JPS60121737A (en) | Element isolating method for semiconductor device | |
| JPS5992547A (en) | Isolation process | |
| JPS61119056A (en) | Manufacture of semiconductor device | |
| JP2643015B2 (en) | Method of manufacturing complete dielectric isolation substrate | |
| JPS6221269B2 (en) | ||
| JP3270912B2 (en) | Method for manufacturing semiconductor device | |
| JPS6185839A (en) | Manufacture of semiconductor integrated circuit | |
| JPH05211230A (en) | Manufacture of semiconductor device | |
| JPS62273750A (en) | Semiconductor device and manufacture of the same | |
| JPH07288279A (en) | Manufacture of dielectric isolation substrate | |
| JPS61125145A (en) | Semiconductor integrated circuit device and its manufacturing | |
| JPH04304655A (en) | Semiconductor device and manufacture thereof | |
| JPH0513560A (en) | Dielectric isolation substrate and its manufacture | |
| JPS6244417B2 (en) | ||
| JPH0616537B2 (en) | Method for manufacturing semiconductor substrate | |
| JPS60752A (en) | Manufacture of semiconductor device | |
| JPS594048A (en) | Fabrication of semiconductor device |