JPH02296352A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02296352A JPH02296352A JP11610789A JP11610789A JPH02296352A JP H02296352 A JPH02296352 A JP H02296352A JP 11610789 A JP11610789 A JP 11610789A JP 11610789 A JP11610789 A JP 11610789A JP H02296352 A JPH02296352 A JP H02296352A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- film
- semiconductor substrate
- polycrystalline silicon
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体素子間を分離す
るだめの凹型溝、即ち[・レンチ分離溝を有する半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a recessed groove, that is, a wrench isolation groove for separating semiconductor elements.
〔従来の技術]
近年、高集積化を目的とした半導体装置では、半導体基
板に形成された素子間を絶縁分離するだめの分離構造と
してトレンチ分離溝が採用されている。従来、この種の
トレンチ分離溝は、半導体基板の表面から深さ方向に狭
い幅寸法の凹型溝(トレンチ)を形成し、この凹型溝の
内面に酸化膜を形成した上で、溝内に多結晶シリコン等
の材料を埋設した構成となっている。[Prior Art] In recent years, trench isolation grooves have been adopted in semiconductor devices aimed at high integration as an isolation structure for insulating and isolating elements formed on a semiconductor substrate. Conventionally, this type of trench isolation trench is formed by forming a trench with a narrow width in the depth direction from the surface of a semiconductor substrate, forming an oxide film on the inner surface of this trench, and then forming a multilayer film inside the trench. It has a structure in which a material such as crystalline silicon is buried.
(発明が解決しようとする課題)
」二連した従来のトレンチ分離溝は、凹溝の内面に形成
した酸化膜は薄く、溝内は殆ど多結晶シリコンで埋設さ
れた状態にある。このため、トレンチ分離溝形成後の熱
処理工程等において、多結晶シリコンと半導体基板との
熱膨張係数の相違により半導体基板に応力が発生し、こ
の応力によって半導体基板の表面に多数の結晶欠陥が生
じて半導体装置の特性に悪影響を与えるという問題があ
る。(Problems to be Solved by the Invention) In the conventional double trench isolation groove, the oxide film formed on the inner surface of the groove is thin, and the inside of the groove is mostly filled with polycrystalline silicon. For this reason, stress is generated in the semiconductor substrate due to the difference in thermal expansion coefficient between polycrystalline silicon and the semiconductor substrate during the heat treatment process after forming the trench isolation groove, and this stress causes many crystal defects on the surface of the semiconductor substrate. There is a problem in that this adversely affects the characteristics of the semiconductor device.
本発明は半導体基板における結晶欠陥の発生を抑制した
半導体装置を提供することを目的とする。An object of the present invention is to provide a semiconductor device in which the occurrence of crystal defects in a semiconductor substrate is suppressed.
本発明の半導体装置は、半導体基板の素子分離領域に形
成したトレンチの内面に酸化膜を形成し、かつこのトレ
ンチ内に多結晶シリコン膜と窒化膜を順次形成して該ト
レンチを埋設している。In the semiconductor device of the present invention, an oxide film is formed on the inner surface of a trench formed in an element isolation region of a semiconductor substrate, and a polycrystalline silicon film and a nitride film are sequentially formed in this trench to bury the trench. .
〔作用]
この構成では、酸化膜、多結晶シリコン膜及び窒化膜の
膜厚を調整することで、1−レンチ溝に埋設した材料全
体の熱膨張係数を半導体基板に略等しくし、応力の発生
を抑制する。[Function] In this configuration, by adjusting the film thicknesses of the oxide film, polycrystalline silicon film, and nitride film, the coefficient of thermal expansion of the entire material buried in the 1-trench groove is made approximately equal to that of the semiconductor substrate, thereby reducing stress generation. suppress.
(実施例〕 次に、本発明を図面を参照して説明する。(Example〕 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
シリコンからなる半導体基板1の表面に絶縁膜2を選択
形成し、この絶縁膜2をマスクにして異方性エツチング
することにより、半導体基板1に幅2μmのトレンチ3
を所要深さに形成している。A trench 3 with a width of 2 μm is formed in the semiconductor substrate 1 by selectively forming an insulating film 2 on the surface of a semiconductor substrate 1 made of silicon, and performing anisotropic etching using the insulating film 2 as a mask.
is formed to the required depth.
そして、このトレンチ3の内側面に0.2μmのシリコ
ン酸化膜4を形成する。また、トレンチ3内には0.5
μmの膜厚の多結晶シリコン膜5を成長し、更にこの内
側に0.3μmのシリコン窒化膜6を成長させてトレン
チ3を埋設し、トレンチ分離溝を構成している。Then, a 0.2 μm silicon oxide film 4 is formed on the inner surface of this trench 3. Also, in trench 3, 0.5
A polycrystalline silicon film 5 with a thickness of .mu.m is grown, and a silicon nitride film 6 with a thickness of 0.3 .mu.m is grown inside the polycrystalline silicon film 5 to fill the trench 3 and form a trench isolation groove.
即ち、シリコン酸化膜4.多結晶シリコン膜5シリコン
窒化膜6のそれぞれのl膜厚1..15t、の比を2:
5:3の比としている。That is, silicon oxide film 4. The film thickness of each of the polycrystalline silicon film 5 and the silicon nitride film 6 is 1. .. 15t, ratio of 2:
The ratio is 5:3.
この構成により、シリコン酸化膜4.多結晶シリコン膜
5.シリコン窒化膜6のそれぞれの熱膨張係数を膜厚の
厚さ比に応じて平均化し、全体として半導体基板1を構
成するシリコンに近い熱膨張係数に調整している。した
がって、l−レンチ分離溝の形成後の熱処理工程によっ
てもI・レンチ分離溝近傍の半導体基板に生しる応力を
低減し、結晶欠陥が抑制できる。With this configuration, the silicon oxide film 4. Polycrystalline silicon film 5. The coefficient of thermal expansion of each silicon nitride film 6 is averaged according to the ratio of the film thicknesses, and the coefficient of thermal expansion of the silicon nitride film 6 as a whole is adjusted to be close to that of silicon constituting the semiconductor substrate 1. Therefore, the stress generated in the semiconductor substrate in the vicinity of the I-wrench isolation trench can also be reduced by the heat treatment step after the formation of the I-wrench isolation trench, and crystal defects can be suppressed.
上述したI・レンチ分離溝を本発明者が実際にシリコン
基板に構成した半導体装置に適用したとごろ、結晶欠陥
を従来の1/2〜1/3に軽減できた。When the present inventor actually applied the above-described I-wrench isolation groove to a semiconductor device formed on a silicon substrate, crystal defects were reduced to 1/2 to 1/3 of the conventional level.
第2図は本発明の第2実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.
この実施例では、半導体基板1に幅2μmのトレンチ3
を形成後、その内側面に0.21zm厚のシリコン酸化
膜4,0.3μm厚の多結晶シリコン膜5.0.3μm
厚のシリコン窒化膜6、再度0.2μm厚の多結晶シリ
コン膜7を順次形成し、トレンチ3を埋設している。In this embodiment, a trench 3 with a width of 2 μm is formed in a semiconductor substrate 1.
After forming, a 0.21 zm thick silicon oxide film 4 and a 0.3 μm thick polycrystalline silicon film 5.0.3 μm are formed on the inner surface.
A thick silicon nitride film 6 and a 0.2 μm thick polycrystalline silicon film 7 are sequentially formed to fill the trench 3.
この実施例においても、少なくともシリコン酸化膜4と
シリコン窒化膜6の膜厚14,16の比を2:3に設定
しており、これにより多結晶シリコン膜5.7を含むI
・レンチ溝内の埋設材Hの全体的な熱膨張係数をシリコ
ンに近づけ、応力の発生による半導体基板1の結晶欠陥
の発生を抑制することができる。In this embodiment as well, the ratio of the film thicknesses 14 and 16 of at least the silicon oxide film 4 and the silicon nitride film 6 is set to 2:3.
- The overall coefficient of thermal expansion of the buried material H in the wrench groove can be made close to that of silicon, and the occurrence of crystal defects in the semiconductor substrate 1 due to the occurrence of stress can be suppressed.
以上説明したように本発明は、半導体基板に設けたトレ
ンチ内に酸化膜、多結晶シリコン膜、窒化膜を順次形成
してl〜レンチを埋設し、かつこれらの膜厚を調整する
ことで、トレンチ溝に埋設した材料全体の熱膨張係数を
半導体基板に略等しくし、熱処理に起因するトレンチ周
辺の結晶欠陥を軽減できる効果がある。As explained above, in the present invention, an oxide film, a polycrystalline silicon film, and a nitride film are sequentially formed in a trench provided in a semiconductor substrate to bury the l~trench, and by adjusting the thickness of these films, This has the effect of making the thermal expansion coefficient of the entire material buried in the trench substantially equal to that of the semiconductor substrate, and reducing crystal defects around the trench caused by heat treatment.
第1図は本発明の第1実施例の縦断面図、第21は本発
明の第2実施例の縦断面図である。FIG. 1 is a longitudinal cross-sectional view of a first embodiment of the present invention, and FIG. 21 is a longitudinal cross-sectional view of a second embodiment of the present invention.
Claims (1)
面に酸化膜を形成し、かつこのトレンチ内に多結晶シリ
コン膜と窒化膜を順次形成して該トレンチを埋設したこ
とを特徴とする半導体装置。1. A semiconductor device characterized in that an oxide film is formed on the inner surface of a trench formed in an element isolation region of a semiconductor substrate, and a polycrystalline silicon film and a nitride film are sequentially formed in this trench to bury the trench. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116107A JP2775845B2 (en) | 1989-05-11 | 1989-05-11 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116107A JP2775845B2 (en) | 1989-05-11 | 1989-05-11 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02296352A true JPH02296352A (en) | 1990-12-06 |
| JP2775845B2 JP2775845B2 (en) | 1998-07-16 |
Family
ID=14678868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1116107A Expired - Lifetime JP2775845B2 (en) | 1989-05-11 | 1989-05-11 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2775845B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100492790B1 (en) * | 1997-06-28 | 2005-08-24 | 주식회사 하이닉스반도체 | Device isolation insulating film formation method of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325947A (en) * | 1986-07-18 | 1988-02-03 | Toshiba Corp | Manufacture of semiconductor device |
-
1989
- 1989-05-11 JP JP1116107A patent/JP2775845B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325947A (en) * | 1986-07-18 | 1988-02-03 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100492790B1 (en) * | 1997-06-28 | 2005-08-24 | 주식회사 하이닉스반도체 | Device isolation insulating film formation method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2775845B2 (en) | 1998-07-16 |
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