JP2811687B2 - Servo device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a servo device for a rotating body provided with a phase error detecting means and a speed error detecting means.

2. Description of the Related Art FIG. 9 shows a typical functional block diagram at the time of reproduction of a servo system of a home video tape recorder. In FIG. 9, reference numeral 1 denotes a cylinder motor for driving a rotary cylinder on which a video signal recording / reproducing head is mounted, and the rotary cylinder has a frequency generator 2 for generating an AC signal having a frequency dependent on the rotation speed thereof. When,
A position detector 3 for generating a position detection signal once per rotation is connected. The output signal of the frequency generator 2 is
The output is supplied to a frequency divider 5 and a controller 6, and the output of the position detector 3 is amplified and shaped by a PG signal amplifier 7, and the output is used as a reset signal. The frequency is supplied to the frequency divider 5. The output signal of the clock generator 9 to which the crystal oscillator 8 is connected is passed through a frequency divider 10 to a cylinder phase counter 11, a cylinder speed counter 12, a capstan phase counter 32, and a capstan speed system. Each of the counters 28 is supplied as a clock pulse.

The number of bits of the cylinder phase system counter 11 is 16 bits. Preset data is supplied from a 16-bit cylinder phase system ROM (read only memory) 13, and the output is supplied to a decoder 14 and a 10-bit latch 15. The first output of the decoder 14 is supplied to the cylinder phase counter 11 as a preset signal.
Is supplied to a delay circuit 16, and the output data of the latch 15 is supplied to a 10-bit DA converter (digital-analog converter) 17. The latch 15
Is supplied with lower 10 bits of data including the LSB (least significant bit) of the 16 bits output data of the cylinder phase ROM 13.

The output of the frequency divider 5 is supplied to the latch 15 as a load signal, the first output of the controller 6 is supplied to an 8-bit latch 18 as a load signal, and the second output is a preset signal. It is supplied to the cylinder speed system counter 12.

The cylinder speed system counter 12 has a 12-bit configuration.Preset data is supplied from a 12-bit cylinder speed system ROM 19, and lower eight bits of data including LSB among the output data are supplied to the latch 18. The output data of the latch 18 is an 8-bit DA converter 20.
Is supplied to

Further, the outputs of the DA converter 17 and the DA converter 20 are combined by a combining circuit 21, and the output signal of the combining circuit 21 is supplied to a cylinder drive circuit 22.

On the other hand, a frequency generator 24 is connected to a capstan motor 23 for running a magnetic tape, and an output signal of the frequency generator 24 is supplied to a controller 26 after being amplified and waveform-shaped by an FG signal amplifier 25. The first output of the controller 26 is supplied to an 8-bit latch 27 as a load signal, and the second output is supplied to a 10-bit capstan speed counter 28 as a preset signal.

Further, the output signal of the control head 29 for reproducing the control signal recorded on the magnetic tape at regular intervals is:
After being amplified and waveform-shaped by the control signal amplifier 30, it is supplied to a 10-bit latch 31 as a load signal.

Clock pulses are supplied from the frequency divider 10 to the capstan speed system counter 28 and the 15-bit capstan phase system counter 32, respectively. The pre-sate signal is supplied from the delay circuit 16 to the capstan phase counter 32, and of the output data, lower 10 bits including LSB are supplied to the latch 31, and the output data of the latch 31 is 10 bits. The bit is supplied to a DA converter 33. The capstan speed system counter 28 is supplied with preset data from a 10-bit capstan speed system ROM 34, and out of the output data, lower 8 bits including LSB is supplied to the latch 27, and the output of the latch 27 is output. The data is supplied to an 8-bit DA converter 35.

Further, the outputs of the DA converter 33 and the DA converter 35 are combined by a combining circuit 36, and the output signal of the combining circuit 36 is supplied to a capstan drive circuit 37.

In FIG. 9, it is assumed that the frequency generator 2 connected to the cylinder motor 1 generates an AC signal of 6 cycles per rotation, and the frequency divider 5 performs a 1/6 frequency dividing operation. In the NTSC specification (standard of television broadcasting adopted in Japan and the United States), the reference rotation speed of the cylinder motor 1 is 1800 rpm, and at this time, the output frequency of the frequency generator 2 is 180 Hz and the position detector The output frequency of No. 3 is 30 Hz. Therefore, the frequency divider 5
A signal having a phase dependent on the rotation phase of the cylinder motor 1 is obtained from the above, and this signal becomes a rotation phase signal. Further, a clock pulse having a constant frequency is supplied to the cylinder phase system counter 11, and the decoder 14 generates an output pulse when a predetermined count value is reached, so that the first output of the decoder 14 is a cylinder phase system counter. The second output becomes a reference phase signal of a capstan phase system via a delay circuit 16 for tracking adjustment. Further, since a control reproduction signal depending on the running phase of the magnetic tape is obtained from the control head 29, the output signal of the control signal amplifier 30 becomes the running phase signal of the capstan phase system.

On the other hand, a rotation speed signal of the rotary cylinder is obtained from the FG signal amplifier 4, and a rotation speed signal of the capstan is obtained from the FG signal amplifier 25.

At the leading edge (leading edge) of the output signal of the FG signal amplifier 4, the controller 6 first generates a load signal for taking the count value of the cylinder speed system counter 12 into the latch 18, and then generates the load signal.
Generates a preset signal. The controller 26 of the capstan speed system also performs the same operation as the controller 6. Therefore, the measurement result of the phase difference between the rotation phase signal of the cylinder and the reference phase signal is held in the cylinder phase system latch 15, and the measurement result of the cycle of the rotation speed signal is held in the cylinder speed system latch 18. The measurement result of the rotation phase difference of the capstan is held in the latch 31 of the capstan phase system, and the measurement result of the cycle of the rotation speed signal of the capstan is held in the latch 27 of the capstan speed system. The output of the latch 15 (measured output of the cylinder phase counter 11) is converted into a DC voltage by a DA converter 17, and the output of the latch 18 (cylinder speed counter
12) are converted into DC voltages by a DA converter 20, and these DC voltages are synthesized by a synthesizing circuit 21 to generate a cylinder rotation error output signal. The cylinder motor 1 is driven via the motor.

The output of the latch 31 (measured output of the capstan phase system counter 32) is converted into a DC voltage by a DA converter 33, and the output of the latch 27 (measured output of the capstan speed system counter 28) is converted to a DC voltage. The DC voltage is converted by the A converter 35, and these DC voltages are
A capstan rotation error output signal is created by the combination by the capstan, and the capstan motor 23 is driven by the capstan via the drive circuit 37 by the error output signal.

Problems to be Solved by the Invention By the way, in FIG.
1. Preset data is supplied from a separate ROM to each of the cylinder speed system counter 12 and the capstan speed system counter 28. These preset data are mainly prepared for double-speed reproduction. For example, in the NTSC specification of the VHS system, the relative speed between the rotating head and the magnetic tape during recording or normal (+ 1x speed) reproduction is almost the same.
The speed is 5.8 m / sec, but when the magnetic tape is run at +9 times the speed of the 2-hour mode (if the controller 26 divides the output signal of the FG signal amplifier 25 by 1/9, the capstan motor 23 becomes 9 times faster). The rotation speed of the magnetic tape is nine times as high as the rotation speed of the magnetic tape.) Since the running direction of the rotating head on the magnetic tape is equal to the normal running direction of the magnetic tape, the relative speed between the rotating head and the magnetic tape is , The frequency of the reproduced horizontal synchronizing signal decreases by about 4.8%, and conversely, when the magnetic tape runs at -9 times speed, the frequency of the reproduced horizontal synchronizing signal increases by about 5.4%. If the frequency of the horizontal synchronizing signal greatly changes, the TV receiver cannot follow the signal and the synchronization is disturbed. Therefore, it is necessary to correct the relative speed so as not to change.
To explain this by taking +9 times speed as an example, in order to correct the relative speed, it is sufficient to prepare preset data such that the count frequency of the cylinder phase system counter 11 becomes 4.8% higher than that during normal reproduction. Speed counter 12 and capstan speed counter
The preset data to be supplied to 28 is also set so that the speed error output becomes zero during the synchronous rotation.

Thus, the cylinder phase system ROM 13 and the cylinder speed system R
The OM 19 and the capstan speed ROM 34 are provided with a number of data corresponding to the type of the required double speed mode. In the NTSC specification, there are three types of recording / reproducing time modes: a 2-hour mode, a 4-hour mode, and a 6-hour mode, so that the number of data (number of addresses) required for each ROM is considerable. For example, in each time mode, ± 15 times speed, ± 9 times speed, ± 5 times speed
Assuming that double speed, ± 3 × speed, ± 2 × speed, ± 1 × speed, 0 × speed (stop) are required, different preset data must be prepared except for + 1 × speed, and the number of addresses of each ROM is required. Is 37 respectively. When a system as shown in FIG. 9 is to be made into an LSI (large-scale integrated circuit),
Not only does the area of the ROM part occupying on the chip and the area of the address decoder part attached thereto become considerably large, but there is a problem that much time is required for the inspection of the ROM data.

As a specific method for solving such a problem, the applicant has previously disclosed in Patent Application No. 191020 in 1984 an arbitrary memory from a memory storing preset data for a cylinder phase system counter. A device that distributes the upper bit data of the number of bits to the cylinder speed counter and the capstan speed counter has been proposed.In this device, the count value of the cylinder phase counter at the time when the detected phase signal arrives is used as phase error data. Because it is configured to take out, not only the preset data is supplied from the common memory to the cylinder phase system counter, but also a decoder for creating the reference phase signal is required, and the setting of this decoder must be changed according to the system specifications. There was an inconvenience of not becoming.

For example, in the NTSC specification, as described above, the output frequency of the position detector 3 during steady operation is 30 Hz, but in the PAL specification adopted in Europe, the output frequency of the position detector 3 is 25 Hz. Since the frequency of the reference phase signal changes accordingly, it is necessary to prepare a decoder for NTSC and a decoder for PAL.

Also, in this device, since the higher order bits of the data from the memory are used as they are for the cylinder speed counter and the capstan speed counter, the actual specifications (FG frequency, clock frequency of each counter, etc.) Requires a controller for matching the data supplied from the memory, and every time the specification is changed, it is necessary to change the configuration of the controller and the method of supplying the clock to the counter.

Therefore, an object of the servo device of the present invention is to simplify the data distribution mechanism for switching the rotation speed of the rotating body more than before, and to realize a system that can flexibly cope with a specification change. .

Still another object of the present invention is to realize an apparatus capable of measuring or detecting a deviation amount or a phase error from a reference phase of a phase signal obtained from a rotating body or the like mainly by software.

Another object of the present invention is to realize an apparatus capable of detecting an error of a speed signal obtained from a rotating body or the like from a reference speed mainly by software.

Means for Solving the Problems In order to solve the above-mentioned problems, in a servo device of the present invention, as a first configuration, measurement data corresponding to a phase difference between a rotation phase signal of a rotating body and a reference phase signal is clock pulsed. A phase difference measuring unit that outputs the count value of the reference phase signal; a memory unit that supplies reference data for generating a cycle of the reference phase signal to the phase difference measuring unit; Phase error calculating means for calculating a phase error by subtracting half the data of the reference data supplied from the means, and a rotational speed signal of the rotator based on the reference data and a clock pulse. Speed error detecting means for calculating an error of the repetition period from the reference value, and the phase error measuring means includes clock pulses equal in number to the reference data supplied from the memory means. A zero detector for detecting that the pulse has been counted and updating the count cycle, outputting the count amount from the start of each count cycle to the arrival of the rotation phase signal as measurement data, and the speed error detection means And a multiplier for multiplying the reference data by a decimal number smaller than one, and outputs difference data between a count amount obtained by counting clock pulses during one cycle of the rotation speed signal and output data of the multiplier. Further, as a second configuration, a memory means in which reference data for generating a reference phase signal of the rotating body is stored, and half-value data having a half size of the reference data supplied from the memory means are provided. A preset first counter, an adder for adding the least significant bit of the half value data and the least significant bit of the reference data, and comparing the count value of the first counter with the output data of the adder, they match. A comparator for presetting the first counter, a first latch for holding a count value of the first counter when a rotation phase signal of a rotating body arrives, and a first latch based on the reference data and a clock pulse. Speed error detecting means for calculating an error of a repetition period of the rotation speed signal of the rotating body from a reference value. Further, as a third configuration, a memory means for storing reference data for generating a reference phase signal of the rotating body, and a half-value data having a half size of the reference data supplied from the memory means A first counter preset by inverting the sign or logic, an adder for adding the count value of the first counter and the least significant bit of the reference data, the half-value data and the output data of the adder And a comparator for presetting the first counter when the two coincide with each other, and the first counter when the rotation phase signal of the rotating body arrives.
A first latch for holding the count value of the counter of the above, and a speed error detecting means for calculating an error from a reference value of a repetition period of the rotation speed signal of the rotating body based on the reference data and the clock pulse. ing.

Further, in order to solve the above-mentioned problem, in the phase difference measuring means of the servo device of the present invention, a counter for counting clock pulses, and an adder to which reference data supplied from the memory means is supplied as one input data. A register that supplies output data of the adder as the other input data of the adder, a latch that holds a count value of the counter each time a phase signal arrives, and a difference between output data of the register and the latch. And an ordering means for causing the adder to perform an addition operation after the operation timing of the latch, and then causing the register to take in input data. It is configured to output as a deviation amount from the reference value of the signal.

Further, in order to solve the above-mentioned problem, in the phase error detecting means of the servo device of the present invention, a first counter which counts clock pulses and a reference data supplied from a memory means is supplied as one input data. An adder, a register that supplies output data of the first adder as the other input data of the first adder, a latch that holds a count value of the counter each time a phase signal arrives, Register and half of the reference data
A second adder for adding half-value data having a size of: a calculator for calculating a difference between the second adder and the output data of the latch; and operating the calculator after the operation timing of the latch. Successively causing the first adder to perform an addition operation, further causing the register to take in input data, and then causing the second adder to perform an addition operation; It is configured to output output data of the arithmetic unit as a phase error amount of the phase signal.

Furthermore, in order to solve the above-mentioned problem, in the speed error detecting means of the servo device of the present invention, a counter for counting clock pulses, a latch for holding a count value of the counter each time a speed signal arrives, A register to which the data held by the latch is transferred each time a speed signal arrives, and an addition wherein reference data supplied from a memory means is supplied as one input data and an output of the register is supplied as the other input data. An arithmetic unit for calculating the difference between the output data of the adder and the latch; and operating the arithmetic unit after the operation timing of the latch and causing the register to take in the input data. Sequence means for causing the arithmetic unit to perform an addition operation, so that output data of the arithmetic unit is output as a speed error amount. It has been made.

According to the servo device of the present invention, the first configuration described above updates the count cycle by the zero detector every time the same number of clock pulses as the reference data supplied from the common memory means are counted, thereby changing the reference phase signal. The phase error is calculated by subtracting the count value at the time of the arrival of the rotation phase signal and the data having a size of half of the reference data, and the data obtained by multiplying the reference data by a decimal number smaller than 1 is used. Similarly, the calculation of the speed error is performed. Further, according to the second configuration or the third configuration, the preset value of the phase-based counter is calculated from the data having a half size of the reference data (hereinafter referred to as half value data) supplied from the common memory. A count end value is generated, and a speed error is calculated.

Further, in the phase difference measuring means of the servo device according to the present invention, the deviation amount of the phase signal from the reference value is calculated based on the count value obtained from the counter prepared as hardware by the above-described operation. It is determined by a subtraction operation.

Further, in the phase error detecting means of the servo device of the present invention, the phase error amount of the phase signal is obtained by the addition operation and the subtraction operation based on the count value obtained from the counter provided as hardware. At the same time, the reference phase is set and the phase error is calculated from the reference data supplied from the memory.

Furthermore, in the speed error detecting means of the servo device of the present invention, according to the above-described configuration, when a speed signal arrives, only one addition operation is performed based on a count value obtained from a counter prepared as hardware. As a result, the speed error is immediately calculated.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a servo device according to an embodiment of the present invention, and the same blocks as those in FIG. 9 are indicated by the same reference numerals. In the system shown in FIG. 1, a common memory is provided in a cylinder phase system counter 11 for measuring a phase difference between a rotation phase signal of the cylinder motor 1 and a reference phase signal.
Preset data is supplied from 38, and output data (count value) of the cylinder phase system counter 11 is supplied to the latch 15 and also to the zero detector 39.
The output of the zero detector 39 is supplied to the cylinder phase counter 11 as a preset command signal, and is also supplied to the delay circuit 16. The data in the common memory 38 is converted to half-value data via a shifter 40 and a complementer 41, the sign of which is inverted, and then supplied to an adder 42. The output data of the latch 15 is also supplied to the adder 42, and the output of the zero detector 39 is supplied to the adder 42 as an addition command signal.

The data of the common memory 38 is supplied via a decimal multiplier 43 to a cylinder speed system counter 12 for measuring a repetition period of the rotation speed signal of the cylinder motor 1. Further, the data of the common memory 38 is supplied to the capstan speed system counter 28 via a decimal multiplier 44. The decimal multiplier 43 and the decimal multiplier 44 each multiply the output data of the common memory 38 by a decimal smaller than 1 by the cylinder speed system counter.
It is supplied to the counter 12 and the capster speed system counter 28, and a multiplication function provided in a general microprocessor can be used. Specifically, by using a 16-bit multiplier that can obtain a 32-bit multiplication result, extracting only the upper 16 bits of the multiplication result,
Bit data can be treated as a decimal smaller than one. For example, the result of multiplying the hexadecimal number [2800] by [8000] is [14000000], but extracting only the upper 16 bits of the multiplication result is [1400], and the multiplier [8000] is the decimal number 0.5. Will be.

Further, the output data of the adder 42 and the output data of the latch 18 to which the output of the cylinder speed system counter 12 is supplied are filtered by a digital filter 45 for each of the speed system and the phase system. , Which are supplied to the DA converter 17 and supplied with the output of the capstan phase counter 32.
And the output data of the latch 27 to which the output of the capstan speed system counter 28 is supplied, the digital filter 46 performs a filtering operation on each of the speed system and the phase system, and then synthesizes them into a digital signal.
-A converter 33 is supplied.

In FIG. 1, the cylinder phase system counter 11,
By the latch 15 and the zero detector 39, the phase difference measurement block 100 that outputs measurement data corresponding to the phase difference between the cylinder rotation phase signal and the reference phase signal as the count value of the clock pulse supplied from the frequency divider 10 is used. Composed of shifters 4
The phase error calculation block 200 for calculating the phase error by subtracting the half value data of the reference data supplied from the common memory 38 from the output data of the phase difference measurement block 100 by the 0, the complementer 41, and the adder 42 is configured. Controller 6, cylinder speed system counter 12, latch 18, decimal multiplier
43, a speed error detection block 300 for calculating an error from a reference value of the repetition period of the cylinder rotation speed signal based on the reference data supplied from the common memory 38 and the clock pulse supplied from the frequency divider 10. Is configured.

The operation of the system shown in FIG. 1 when the VTR is in the playback state will be briefly described. For convenience of explanation, specific numerical values are used, and here, the output frequency of the clock generator 9 is the color in the NTSC specification. 357 of the frequency of the subcarrier signal
It is assumed that the signal is the same as 9.545 kHz. The signal of 894.886 kHz, which is frequency-divided by the frequency divider 10, is supplied to the cylinder phase counter 11 and the capstan phase counter 32 as clock pulses, and It is assumed that the frequency-divided signal of 223.722 kHz is supplied to the cylinder speed counter 12 and the capstan speed counter 28 as a clock pulse.

The ratio between the count period of the cylinder phase system counter 11 and the count period of the cylinder speed system counter 12 during steady rotation is equal to the frequency ratio of the cylinder FG signal and the cylinder PG signal, and is 6 in the system configuration of FIG. Since the frequency ratio of the clock pulse is 4, the count amount per count cycle of the cylinder phase counter 11 and the cylinder speed counter 12 has a difference of 24 times.

Here, each of the counters counts down in the direction of decreasing the count value immediately after the preset is performed, and the zero detector 39 determines that the count value of the cylinder phase counter 11 is [00 ... 000]. ], An output is generated, the preset value of the cylinder phase system counter 11 is Np, and the cylinder speed system counter 12
Is set to Ns.

The count value of the cylinder phase counter 11 is [00 ...
… 000], the cylinder speed counter 12 is self-preset, while the count value is near [00 …… 000] during steady rotation, and the leading edge of the cylinder FG signal arrives. Considering that re-presetting is performed, the following equation is established.

That is, to obtain the preset data Ns for the cylinder speed system counter 12 based on the preset data Np for the cylinder phase system counter 11, 0.0417 (1/1 /
24). Specifically, the common memory shown in FIG.
A decimal multiplier 43 multiplies the preset data Np supplied from 38.

Also, when reproducing the VTR, the capstan motor 2
Since 3 rotates in synchronization with the cylinder motor 1, the capstan speed system counter 28 can also receive the preset data from the common memory 38 via the decimal multiplier 44 as shown in FIG. For example, assuming that the frequency of the capstan FG signal at the time of steady rotation is 1080 Hz, the ratio of the count cycle of the cylinder phase counter 11 to the count cycle of the capstan speed counter 28 is 36, and the frequency ratio of both clock pulses is Is 4, the count amount per count cycle of the cylinder phase system counter 11 and the capstan speed system counter 28 has a difference of 144 times.
The following equation is established between the preset value Np and the preset value Nq of the capstan speed system counter 28.

Therefore, in order to obtain the preset data Nq for the capstan speed system counter 28 based on the preset data Np for the cylinder phase system counter 11, the decimal multiplier 44 shown in FIG. 144).

Now, the preset data Np supplied from the common memory 38 is logically shifted rightward by the shifter 40 so that its value is halved, and the sign is inverted by the complementer 41. The output signals of the frequency generator 2 and the position detector 3 connected to the cylinder motor 1 are amplified and waveform-shaped by the FG signal amplifier 4 and the PG signal amplifier 7, respectively, and supplied to the frequency divider 5. From the frequency divider 5, a rotation phase signal synchronized with the output signal of the frequency generator 2 is obtained. At the leading edge of the rotation phase signal, the count value of the cylinder phase system counter 11 is latched.
, And the held data is added by the adder 42 to the output data of the complementer 41. Therefore, the adder 42 outputs a result obtained by subtracting the half value data of the preset data Np from the data held in the latch 15. The output data of the adder 42 is supplied to a digital filter 45 as cylinder phase system error detection data.

On the other hand, the speed signal from the FG signal amplifier 4 is supplied to the controller 6 and the count value of the cylinder speed system counter 12 is latched every time the leading edge thereof arrives.
After that, the cylinder speed system counter 12 is preset. The output data of the latch 18 is supplied to the digital filter 45 as error detection data of the cylinder speed system.

The digital filter 45 performs a filtering operation on the error detection data of the speed system and the error detection data of the phase system, synthesizes the data, and sends the resultant data to the DA converter 17. In the DA converter 17, output data from the digital filter is converted into a DC voltage and then sent to the cylinder drive circuit 22. by this,
The servo system operates so that the phase difference between the reference phase signal generated from the preset data Np and the rotation phase signal obtained from the frequency divider 5 becomes 180 °. FIG. 2 is a signal waveform diagram of a main part showing these states, and FIG. 2A is a diagram showing a state of a change in a count value of a reference phase signal (cylinder phase system counter 11) generated from preset data Np. 2B is a rotation phase signal obtained from the frequency divider 5, FIG. 2C is a view showing a change in the count value of the capstan speed system counter 28, and FIG. 2D is an FG signal amplifier. 4 is the speed signal obtained from FIG. As can be seen from FIG. 2, when the arrival timing of the leading edge of the rotation phase signal is later than the time t1, the count value taken into the latch 15 becomes smaller than half of the preset data Np, and the calculation by the adder 42 is performed. The result is negative. Conversely, when the timing of the arrival of the leading edge of the rotation phase signal is earlier than the time t1, the count value taken into the latch 15 becomes larger than half of the preset data Np, and the calculation result in the adder 42 becomes a positive value. Become. When the rotation speed of the cylinder motor 1 decreases and the period of the speed signal increases, the count value taken into the latch 18 becomes [000...
0] and becomes a negative value, but when the rotation speed increases and the period of the speed signal is shortened, the count value taken into the latch 18 becomes a positive value.

As is clear from the comparison between the apparatus shown in FIG. 1 and the apparatus shown in FIG. 9, in the servo apparatus of the present invention, a reference phase signal is generated and a phase error is calculated from reference data supplied from a common memory. At the same time, the speed error is calculated, and the data distribution mechanism for switching the rotation speed of the rotating body can be simplified as compared with the conventional case.

By the way, in the embodiment shown in FIG.
Requires two decimal multipliers 43 and 44 to distribute the preset data to the cylinder speed counter 12 and the capstan speed counter 28, but the system of FIG. 1 is actually realized by a microprocessor. The decimal multipliers 43 and 44, the cylinder speed system counter 12, the capstan speed system counter 28, the cylinder phase system counter 11, the capstan phase system counter 32, and the accompanying Since the controller and the like are all realized by a program built in the microprocessor, or the specific hardware (for example, an arithmetic logic unit) provided in the microprocessor is used by the program,
This does not impose too much of a burden, and increases flexibility in changing specifications.

Next, FIG. 3 is a block diagram showing another embodiment of the present invention, which is a block centering on a phase difference measurement block 100, a phase error calculation block 200 and a speed error detection block 300 which are main parts of the servo device. It is shown.

In the apparatus shown in FIG. 3, a common counter 47 for counting clock pulses, an adder 48 for adding the count value of the common counter 47 and reference data supplied from a common memory 38, and an output of the adder 48 Register 49 supplied
And the common counter 47 every time a rotation phase signal arrives.
The latch 50 that holds the count value of the register 49, the complementer 51 that determines the difference between the output data of the register 49 and the output data of the latch 50, and the adder 52, and the count value of the common counter 47 matches the output of the adder 48. A phase difference measurement block 100 is constituted by a controller 53 that causes the register 49 to update the data at the time and the adder 48 to perform the adding operation.

Further, a shifter 40 for shifting the reference data supplied from the common memory 38 to the right to obtain half value data, a complementer 41 for obtaining a difference between output data of the shifter 40 and output data of the phase difference measurement block 100, and an adder A phase error calculation block 200 is constituted by 42, a decimal multiplier 43 for multiplying the reference data by a decimal smaller than 1, a latch 54 for holding a counter value of a common counter 47 every time a rotation speed signal arrives, A register 55 for taking in output data of the latch 54 every time a speed signal arrives; a complementer 56 for finding a difference between the register 55 and the output data of the latch 54
And an adder 57, the decimal multiplier 43, and the adder 57.
A speed error detection block 300 is constituted by the complementer 58 for obtaining the difference between the output data and the adder 59. In the apparatus of FIG. 3, the delay elements 60, 61, 62, 63, 64, 6
Reference numeral 5 denotes a processing delay caused by sequential processing by software, in other words, a processing procedure.

The operation of the phase difference measurement block 100 and the speed error detection block 300 in FIG. 3 will be described. First, common counter 4
Reference numeral 7 denotes a self-propelled up counter which is different from the cylinder phase counter 11 or the cylinder speed counter 12 shown in FIG. Although the initial value of the output data of the adder 48 is undefined, the common counter 47 updates the count value every moment, so the controller 53 adds the count value when the count value becomes equal to the output data of the adder 48. An add command signal is sent to the device 48, and the count value at that time and the common memory 38
Is added to the reference data. The result of the addition is compared by the controller 53 with the count value of the common counter 47, and when the values match, the reference data is added again. Therefore, the output data of the adder 48 is successively increased by a numerical value equal to the reference data supplied from the common memory 38. Of course, adders
Since the bit length of the output unit 48 is finite, the output data decreases again when an overflow occurs, but the output data of the common counter 47 supplied to the controller 53 is also the bit length of the output unit of the adder 48. Can be compared under the same conditions.

On the other hand, when the leading edge of the rotation phase signal from the frequency divider 5 arrives, the count value at that time is taken into the latch 50, and subsequently, the output data of the latch 50 is first stored in the register 49. Data subtraction is performed by the complementer 57 and the adder 52. Further, in the phase error calculation block 200, the half value data of the reference data is subtracted from the subtraction result, the result is output as phase error detection data, and the addition result in the adder 48 is transferred to the register 49. You. The register 49
Is used as reference phase data when the next leading edge of the phase detection signal arrives.

In the device shown in FIG. 3, when the n-th leading edge of the rotation phase signal arrives, the reference phase data stored in the register 49 is Dn, and the count value taken into the latch 50 at that time is Cn. The following equation holds between the reference data Np supplied from the memory 38.

Np = D (n + 1) -Dn (3) The output data Pn of the adder 42 is Similarly, the output data P (n) of the adder 42 when the (n + 1) th leading edge of the rotation phase signal arrives
+1) Considering that the servo system operates so that the phase error data becomes 0, from the expressions (3) to (5), the difference between Cn and Dn becomes equal to one half of Np, and furthermore, Cn and C (n +
Control is performed so that the difference in 1) is equal to Np. That is, the servo system operates so that the phase difference between the rotation phase signal and the reference phase signal (given as reference data from the common memory 38) is always 180 °. Therefore, the phase difference measurement block 100 shown in FIG. 3 also has the same function as the phase difference measurement block 100 shown in FIG. When the phase difference measurement block 100 of FIG. 3 is used instead of the phase difference measurement block 100 of FIG. 1, the output of the controller 53 may be supplied to the delay circuit 16.

Next, the operation of the speed error detection block 300 in FIG. 3 will be described. When the leading edge of the speed signal supplied from the FG signal amplifier 4 arrives, the count value of the common counter 47 at that time is taken into the latch 54, and subsequently, taken into the latch 54 by the complementer 56 and the adder 57. The subtraction of the counted value and the data stored in the register 55 is performed, and the output data of the decimal multiplier 43 is subtracted from the result of the subtraction. Then latch
The count value stored in 54 is transferred to register 55.
Thereafter, the same operation is repeated every time the leading edge of the speed signal arrives. Therefore, the count value of the clock pulse counted by the common counter 47 from the leading edge of the speed signal to the next leading edge is obtained from the adder 57,
Speed error data is obtained from the adder 59.

The main part of the servo device shown in FIG. 3 is composed of a phase difference measurement block 100 and a speed error detection block 300 with the intention of increasing flexibility in changing specifications by incorporating a lot of software processing. Although the common counter 47 of both blocks is prepared as peripheral hardware of the microprocessor, all other elements in each block are realized by software processing. That is, each adder is realized by an addition instruction of a microprocessor, a register and a latch are realized by a memory operation instruction or a register operation instruction, each complementer is realized by a sign inversion instruction alone, and a dry number is calculated by a subtraction instruction. An arithmetic unit in which an adder and an adder are combined is realized. Further, the controller 53 constituting the phase difference measurement block 100 can be realized by using a comparison instruction of a microprocessor.

As described above, the servo apparatus shown in FIGS. 1 and 3 outputs the phase difference measurement data corresponding to the phase difference between the rotation phase signal of the cylinder motor 1 and the reference phase signal as the count value of the clock pulse. Block 100, a common memory 38 that supplies reference data for generating a cycle of the reference phase signal to the phase difference measurement block 100, and output data of the phase difference measurement block 100, which is supplied from the common memory 38. A phase error calculation block 200 for calculating a phase error by subtracting half value data of the reference data, and an error from a reference value of a repetition period of the rotation speed signal of the cylinder motor 1 based on the reference data and the clock pulse. Speed error detection block 300 for calculating the phase error calculation block 200 and the speed error detection block 300
And a cylinder drive circuit 22 for driving the cylinder motor 1 with an error output signal obtained by synthesizing the output data by the digital filter 45.

Further, in the servo device shown in FIG. 1, the cylinder phase counter 11 for counting clock pulses and the number of clock pulses equal to the reference data supplied from the common memory 38 are counted by the cylinder phase counter 11. And a zero detector 39 for detecting and updating the count cycle of the cylinder phase system counter 11, and the count amount of the cylinder phase system counter 11 from the start of each count cycle to the arrival of the rotation phase signal as measurement data. A phase difference measurement block is configured by the latch 15 that holds the data.The shifter 40 obtains half-value data by shifting the reference data supplied from the common memory 38 to the right, and the output data of the shifter 40 and the output data of the latch 15. A phase error calculation block 200 is constituted by the complementer 41 for obtaining the difference and the adder 42, and A decimal multiplier 43 for multiplying data by a decimal number smaller than 1, a cylinder speed system counter 12 for counting clock pulses during one cycle of the rotation speed signal, a count amount of the cylinder speed system counter 12 and the decimal multiplier 43 The speed error detection block 300 is constituted by the latch 18 which holds the difference data from the output data of the speed error detector 300.

Further, in the servo device shown in FIG. 3, a common counter 47 for counting clock pulses, an adder 48 for adding the count value of the common counter 47 and reference data supplied from a common memory 38, A register 49 to which the output of the adder 48 is supplied, and a latch 50 for holding the count value of the common counter 47 each time a rotation phase signal arrives
A complementer 51 and an adder 52 for calculating a difference between output data of the register 49 and the latch 50, and the common counter.
A controller that causes the adder 48 to perform an addition operation when the count value of 47 matches the output of the adder 48.
53 constitutes the phase difference measurement block 100. Further, a shifter 40 for shifting the reference data supplied from the common memory 38 to the right to obtain half-value data, a complementer 41 for obtaining a difference between the output data of the shifter 40 and the output data of the phase difference measurement block 100, and an adder 42 Constitutes a phase error calculation block 200, a decimal multiplier 43 for multiplying the reference data by a decimal number smaller than 1, and a latch 54 for holding a count value of a common counter 47 every time a rotation speed signal arrives.
A register 55 for taking in the output data with the latch 54 every time the rotation speed signal arrives, a complementer 56 for obtaining a difference between the output data of the register 55 and the output data of the latch 54, an adder 57, and the decimal multiplier A speed error detection block is constituted by the complementer 58 for obtaining the difference between the output data of the adder 57 and the output data of the adder 57 and the adder 59.

Next, FIG. 4 shows a simplified configuration of the phase difference measurement block 100 and the speed error detection block 300 of FIG. 3, and a common counter 47 for counting clock pulses,
An adder 66 to which the reference data supplied from the common memory 38 is supplied as one input data, a register 49 for delaying the output data of the adder 66 and supplying the data as the other input data of the adder 66, A latch 50 for holding the count value of the common counter 47 every time a phase signal arrives
And a complementer 51 for calculating the difference between the output data of the register 49 and the latch 50 and an adder 52 constitute a phase difference measurement block 100, and the output data of the adder 52 deviates from the reference value of the phase signal. Output as a quantity. Also,
The phase difference measurement block 100, a shifter 40 for obtaining half value data of the reference data from the common memory 38, a complementer 41 for obtaining a difference between the half value data and the output data of the adder 52, and an adder 42 for calculating a phase error. Detection is performed, and the output data of the adder 42 is output as the phase error amount of the phase signal.

The apparatus shown in FIG. 4 is characterized in that the other addition data of the adder to which the reference data is supplied from the common memory 38 is supplied from a register 49. This is the third
In the device shown in the figure, when the output data of the adder 48 and the count value of the common counter 47 become equal, the controller 53 sends an addition command signal to the adder 48, and the leading edge of the phase signal arrives. Is added to the register 49. That is, the controller 53
Focusing on the fact that the count value at the time of sending the addition command signal and the input data of the register 49 are equal, and this input data is stored in the register 49 when the leading edge of the phase detection signal arrives, The output data of the register 49 is supplied as input data of the adder 66 instead of the count data. This eliminates the need to perform the addition process while monitoring the count data, which changes the value every moment and the processing load on the microprocessor is large, and, as shown in FIG. Every time the adder 52 executes a process of calculating the amount of phase deviation,
The calculation of the phase error is performed in step (1), the adder 66 performs the addition processing, and then the register 49 is fetched the addition result, whereby the controller 53 in FIG. 3 becomes unnecessary. When the delay circuit shown in FIG. 1 is used, the comparator shown in FIG.
The necessary signals can also be supplied from 71.

The speed error detection block 300 shown in FIG.
A common counter 47 for counting clock pulses, a latch 54 for holding a count value of the common counter 47 each time a speed signal arrives, and a register to which data held in the latch 54 is transferred each time the speed signal arrives 55,
Reference data supplied from the common memory 38 is supplied as one input data, and the output of the register 55 is supplied as the other input data, and the difference between the output data of the adder and the latch is obtained. It comprises a complementer 69 and an adder 70, and the output data of the adder 70 is output as a speed error amount. By employing this configuration, the number of complementers is reduced to one as compared with the speed error detection block 300 shown in FIG.

Next, the embodiment of FIG. 5 simplifies the phase error detection section based on the same concept as the speed error detection block 300 shown in FIG. 4, and includes a common counter 47 for counting clock pulses. An adder in which reference data supplied from the common memory 38 is supplied as one input data
66, a register 49 that delays the output data of the adder 66 and supplies it as the other input data of the adder 66,
A latch 50 for holding the count of the common counter 47 each time a phase signal arrives, an adder 72 for adding the register 49 and half value data of the reference data, and the adder
A compensator 73 for obtaining a difference between the output data of the latch 50 and the output data of the latch 50 and an adder 74 are provided, and the output data of the adder 74 is output as a phase error amount of a phase signal.

In the apparatus shown in FIG. 5, the number of the plurality of devices constituting the phase error detecting section is reduced by one as compared with the apparatus shown in FIG.

FIG. 6 is a block diagram of a servo device according to another embodiment of the present invention. The common memory 38 stores reference data for generating a reference phase signal of the cylinder motor 1, and the common memory 38. Cylinder phase counter that presets the half value data of the reference data supplied from
11, an adder 75 for adding the least significant bit of the half value data and the reference data, and the cylinder phase counter 11
The comparator 76 compares the output data of the adder 75 with the count value of
A first latch 15 for holding the count value of the cylinder phase system counter 11 at the time of arrival of the rotation phase signal of
A speed error detection block 300 for calculating an error from a reference value of a repetition period of the rotation speed signal of the cylinder motor based on the reference data and the clock pulse; and output data of the latch 15 and the speed error detection block 300. An output signal obtained by synthesizing output data from the digital filter 45 with the digital
And a cylinder drive circuit 22 for driving the motor. further,
A decimal multiplier 43 for multiplying the reference data supplied from the common memory 38 by a decimal number smaller than 1;
Output data of the cylinder speed system counter 12 for counting clock pulses during one cycle of the rotation speed signal, and difference data between the count amount of the cylinder speed system counter 12 and the output data of the decimal multiplier 43. The speed error detection block 300 is constituted by the latch 18 held. The supply of preset data from the common memory 38 to the cylinder phase counter 11 is performed via a shifter 77 that logically shifts input data to the right, and the supply of half-value data to the adder 76 is performed by a shifter 78. Is performed via Also, the cylinder phase system counter
The counter 11 and the cylinder speed counter 12 are both down-counting counters. Therefore, the count data of the cylinder phase counter 11 is supplied to the comparator 76 via a complementer 79.

In the device shown in FIG. 6, the cylinder phase system is a counter.
The eleven preset data are configured to be half value data of the reference data Np supplied from the common memory 38.
Therefore, assuming that a clock pulse having the same frequency as that of the apparatus shown in FIG.
Counts over [000... 00] and counts over. When the data whose sign is inverted by the complementer 79 becomes equal to the output data of the adder 75, the comparator 76 resets the preset value. Done. The adder 75 converts the LS of the reference data into half value data.
The reason why B is added is to compensate for dropped bits in shifter 77 and shifter 78. That is, the reference data
If Np is even, the right-shifted result is exactly half the value, but if it is odd, the LSB value is lost by right-shifting. For this reason, the LSB is added to one of the outputs of the shifter 77 and the shifter 78 so that the sum of the two outputs is always equal to Np.

FIG. 7 shows another embodiment of the present invention in which an up-counting type counter is used for the phase system and the speed system.
In FIG. 7, the cylinder phase system counter 80 and the cylinder speed system counter 81 are both up counters, and negative preset data is supplied to the cylinder phase system counter 80 via a shifter 77 and a complementer 82. The cylinder phase system counter 80 starts counting up from a count value obtained by subtracting the half value data of the reference data Np from [00... 00], and the cylinder speed system counter 81 also controls the decimal multiplier 43 and the complementer 83. Negative preset data is supplied via the terminal. When the count value of the cylinder phase-based counter 80 increases and the value obtained by adding the LSB of the reference data to the count value becomes equal to the half value data of the reference data, that is, the output data of the adder 84 becomes the output data of the shifter 77. , The comparator 76 performs a preset. In the apparatus of FIG. 6, the LSB of the reference data is added to the output data of the shifter 78. In the apparatus of FIG. 7, the same effect is obtained by adding the LSB of the reference data to the count value of the cylinder phase counter 80. It has gained.

By the way, in each of the embodiments described above, a complementer is used to invert the sign of data. However, when the apparatus is mainly composed of hardware, an inverter (logical inverter) is more suitable than a complementer. The configuration is simplified. In the embodiment shown in FIG. 8, inverters 85 and 86 are used instead of the complementers 82 and 83 in FIG.

As described above, in the apparatus shown in FIG. 7 or FIG. 8, the common memory 38 storing the reference data for generating the reference phase signal of the cylinder motor and the half value data of the reference data supplied from the common memory 38 are provided. Is preset, a cylinder phase system counter 80, an adder 84 that adds the count value of the cylinder phase system counter 80 and the least significant bit of the reference data, and compares the half value data and the output data of the adder 84. A comparator 76 that presets the cylinder phase counter 80 when the two match.
A latch 15 for holding the count value of the cylinder phase counter 80 at the arrival of the rotation phase signal of the cylinder motor, and a reference value for a repetition period of the rotation speed signal of the cylinder motor based on the reference data and the clock pulse. Speed error detection block 300 for calculating the error from the speed
And a cylinder drive circuit 22 for driving the cylinder motor 1 by an error output signal obtained by combining output data from the latch 15 and the speed error detection block 300 by a digital filter 45.

In the apparatus of FIG. 7, the sign of half value data of the reference data supplied from the common memory 38 is inverted and preset to the cylinder phase counter 80, and a decimal multiplier for multiplying a decimal smaller than the reference data 1 is provided. 43, data obtained by inverting the sign of the output data of the decimal multiplier 43, and a cylinder speed counter 81 for counting clock pulses during one cycle of the rotation speed signal; and a count amount of the cylinder speed counter 81. And the decimal upper calculator
The speed error detection block 300 is constituted by the latch 18 holding the difference data from the output data of 43.

Further, in the apparatus shown in FIG. 8, the logic of the half value data of the reference data supplied from the common memory 38 is inverted and supplied as preset data to the cylinder phase counter 80, and a decimal number smaller than 1 is added to the reference data. A decimal multiplier 43 to be multiplied and data obtained by inverting the logic of the output data of the decimal multiplier 43 are preset, and the rotation speed signal 1
A speed error detection block 300 is constituted by a cylinder speed system counter 81 that counts clock pulses during a period, and a latch 18 that holds difference data between the count amount of the cylinder speed system counter 81 and the output data of the decimal multiplier 43. doing.

As is clear from the above description, the servo device of the present invention, as shown in the embodiment in FIGS. 1 and 3, has the rotational phase signal of the rotating body such as the cylinder motor 1 and the reference phase signal. Phase difference measurement means (phase difference measurement block 100) for outputting measurement data corresponding to the phase difference between the two as a count value of a clock pulse, and the phase difference measurement means for outputting reference data for generating a cycle of the reference phase signal. And reference data supplied from the memory means based on output data of the phase difference measuring means.
A phase error calculating means (phase error calculating block 200) for calculating a phase error by subtracting data of one-half size; and repeating a rotation speed signal of the rotating body based on the reference data and a clock pulse. Speed error detection means (speed error detection block 300) for calculating an error from the cycle reference value
And drive means (cylinder drive circuit 22) for driving the rotating body by an error output signal obtained by combining output data of the phase error calculation means and the speed error detection means. In order to reset a conventional cylinder phase counter (down counter), a decoder designed with a reset value for each device specification (a predetermined value that has passed 0) is not necessary, and a common memory is used. A reference phase signal having the same number of clock pulse count cycles as the supplied reference data is generated, and a difference between the reference data and the half value data of the reference data is obtained without detecting the phase error based on 0 value. To enable phase error detection, and use a conventional speed-based counter to use the upper bits of data from the common memory as is. In order to eliminate the need for specification changes such as a controller that has been designed to be matched, 1 in the reference data
By providing a multiplier for multiplying a smaller decimal number, the calculation of the speed error can be performed using the reference data. As a result, the mechanism for distributing data from memory for switching the speed of the rotating body is simplified more than before, and it is possible to flexibly respond to changes in specifications only by changing the data in the memory and the coefficients of the multiplier. System that can be realized,
It has a great effect.

Further, as shown in the embodiment of FIG. 6, the servo device of the present invention includes a memory means (common memory 38) storing reference data for generating a reference phase signal of the rotating body, and the memory means. A first counter (cylinder phase counter 11) in which half-value data of half the size of the supplied reference data is preset, and an adder for adding the half-value data and the least significant bit of the reference data 75, a comparator 76 for comparing the count value of the first counter with the output data of the adder and presetting the first counter when they match, and an arrival time of the rotation phase signal of the rotating body. A first latch 15 for holding a count value of the first counter, and a reference value for a repetition period of a rotation speed signal of the rotating body based on the reference data and a clock pulse. A speed error detecting means (speed error detecting block 300) for calculating the error, and a drive for driving the rotating body by an error output signal obtained by combining output data of the first latch and the speed error detecting means. Means (cylinder drive circuit 22) for generating a preset value and a count end value of a phase-based counter from half value data of reference data supplied from a common memory, Since the speed error is calculated, the data distribution mechanism for switching the rotation speed of the rotating body can be simplified more than before, and a system that can flexibly respond to specification changes can be realized. It has an effect.

Further, as shown in the embodiment in FIGS. 7 and 8, the servo device of the present invention has a memory means (common memory 38) storing reference data for generating a reference phase signal of the rotating body. A first counter (cylinder phase counter 80) in which half-value data of half the size of the reference data supplied from the memory means is preset, a count value of the first counter and the reference data An adder 84 that adds the least significant bit of the adder, a comparator 76 that compares the half-value data and the output data of the adder and presets the second counter when they match, and an adder 84, A first latch 15 for holding a count value of the first counter at the time of arrival; The rotating body is driven by a speed error detecting means (speed error detecting block 300) for calculating an error from a reference value, and an error output signal obtained by combining output data of the first latch and the speed error detecting means. And a drive unit (cylinder drive circuit 22) for generating a preset value and a count end value of a phase counter from half value data of reference data supplied from a common memory. At the same time, since the speed error is calculated, a data distribution mechanism for switching the rotation speed of the rotating body can be simplified more than before, and a system that can flexibly cope with a change in specifications can be realized. It works.

As shown in the embodiment of FIG. 4, the servo device of the present invention has a counter (common counter 47) for counting clock pulses and one of the reference data supplied from the memory means (common memory 38). An adder 66 supplied as input data; and a register 49 for delaying output data of the adder and supplying the delayed data as the other input data of the adder.
A latch 50 for holding the count value of the counter each time a phase signal arrives; an arithmetic unit for calculating the difference between the output data of the register and the latch (in the embodiment of FIG. 4, a complementer 51 and an adder 52)
And means for causing the adder to perform an addition operation after the operation timing of the latch, and then to fetch input data into the register (the delay elements 60, 61, 62 in the embodiment of FIG. 4). , 67). The output data of the arithmetic unit is output as a deviation amount from a reference value of the phase signal. Since the amount of deviation of the phase signal from the reference value is obtained by adding and subtracting operations based on the obtained count value, the amount of deviation of the phase signal from the reference phase should be measured mainly by software. A device capable of performing the above-mentioned operations can be realized, and a great effect can be obtained.

Further, as shown in the embodiment of FIG. 5, the servo device of the present invention has a counter (common counter 47) for counting clock pulses and one of the reference data supplied from the memory means (common memory 38). A first adder 66 supplied as input data, a register 49 for supplying output data of the first adder as the other input data of the first adder, and a register 49 for receiving a phase signal every time a phase signal arrives. A latch 50 for holding a count value of a counter, a second adder 72 for adding the register and half-value data having a half size of the reference data, and a latch 50 for the second adder and the latch. An arithmetic unit for obtaining a difference between output data (in the embodiment shown in FIG. 5, the arithmetic unit is constituted by a complementer 73 and an adder 74), and the arithmetic unit is operated after the operation timing of the latch. First Ordering means for causing an adder to perform an addition operation, further causing the register to take in input data, and then causing the second adder to perform an addition operation (a delay element in the embodiment of FIG. 5) 6
0, 62, 67, and a delay element inserted between the register 49 and the adder 72) to output the output data of the arithmetic unit as a phase error amount of the phase signal. Since the amount of deviation from the reference value of the phase signal is obtained by an addition operation and a subtraction operation based on the count value obtained from a counter prepared as hardware, the reference value of the phase signal is obtained. A device capable of measuring the amount of deviation from the phase mainly by software can be realized, and a great effect can be achieved.

As shown in the embodiment of FIG. 4, the servo device of the present invention comprises a counter (common counter 47) for counting clock pulses, and a latch 54 for holding the count value of the counter every time a speed signal arrives. A register 55 to which data held by the latch is transferred each time the speed signal arrives, and reference data supplied from a memory means (common memory 38) are supplied as one input data, and an output of the register is supplied to the other. Adder supplied as input data for
68 and an arithmetic unit for calculating the difference between the output data of the adder and the latch (in the embodiment of FIG. 4, a complementer 69 and an adder
And an ordering means (operation 70) for operating the arithmetic unit after the operation timing of the latch, causing the register to take in input data, and then causing the adder to perform an addition operation. 4 is constituted by delay elements 63, 64, and 65), and the output data of the arithmetic unit is output as a speed error amount, and is prepared as hardware. When the speed signal arrives based on the count value obtained from the counter, the speed error is immediately calculated by one calculation operation by the arithmetic unit. The detection can be performed mainly by software, and a great effect is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a servo device showing one embodiment of the present invention, FIG. 2 is a signal waveform diagram of a main part of the device of FIG.
8 are block diagrams showing another embodiment of the present invention, and FIG. 9 is a block diagram showing a conventional example. 1 ... Cylinder motor, 11,80 ... Cylinder phase system counter, 12,81 ... Cylinder speed system counter, 15,50,54 ...
... Latch, 22 ... Cylinder drive circuit, 38 ... Common memory, 43 ... Decimal multiplier, 47 ... Common counter, 49,55 ...
... registers, 66,68,72,75,84 adder, 76 comparator, 100 phase difference measurement block, 200 phase error calculation block, 300 speed error detection block.

Claims (9)

(57) [Claims] 1. A phase difference measuring means for outputting measurement data according to a phase difference between a rotation phase signal of a rotating body and a reference phase signal as a count value of a clock pulse, and for generating a period of the reference phase signal. Memory means for supplying reference data to the phase difference measuring means; and a phase error by subtracting half the data of the reference data supplied from the memory means from output data of the phase difference measuring means. Phase error calculating means for calculating, a speed error detecting means for calculating an error from a reference value of a repetition period of the rotation speed signal of the rotating body based on the reference data and the clock pulse,
Driving means for driving the rotating body by an error output signal obtained by combining output data of the phase error calculating means and the speed error detecting means, wherein the phase difference measuring means is supplied from the memory means It has a zero detector that updates the count cycle by detecting that the number of clock pulses equal to the reference data has been counted, and outputs the count amount from the start of each count cycle to the arrival of the rotation phase signal as measurement data. The speed error detecting means has a multiplier for multiplying the reference data by a decimal number smaller than 1, and calculates a difference between a count amount obtained by counting clock pulses during one cycle of the rotation speed signal and output data of the multiplier. Servo device that outputs difference data. 2. A phase difference measuring means for outputting measurement data corresponding to a phase difference between a rotation phase signal of a rotator and a reference phase signal as a count value of a clock pulse, and for generating a cycle of the reference phase signal. Memory means for supplying reference data to the phase difference measuring means; and a phase error by subtracting half the data of the reference data supplied from the memory means from output data of the phase difference measuring means. Phase error calculating means for calculating, a speed error detecting means for calculating an error from a reference value of a repetition period of the rotation speed signal of the rotating body based on the reference data and the clock pulse,
A driving unit for driving the rotating body with an error output signal obtained by combining output data of the phase error calculation unit and the speed error detection unit, wherein the phase difference measurement unit is a common counter that counts clock pulses. An adder for adding a count value of the common counter and reference data supplied from a memory means, a first register to which an output of the adder is supplied;
A first latch for holding a count value of the common counter each time a rotation phase signal arrives, a first arithmetic unit for obtaining a difference between output data of the first register and the first latch, and A servo device that causes the adder to perform an addition operation when the count value of the counter matches the output of the adder. 3. A speed error detecting means, comprising: a multiplier for multiplying the reference data by a decimal number smaller than 1; a second latch for holding a count value of a common counter each time a rotation speed signal arrives; A second register for taking in output data of the second latch every time a signal arrives, a second computing unit for calculating a difference between the second register and the output data of the second latch, and the multiplier 3. The servo device according to claim 2, further comprising a third calculator for calculating a difference between the output data of the second calculator and the third calculator. 4. A memory means for storing reference data for generating a reference phase signal of a rotating body, and half-value data having a half size of reference data supplied from said memory means are preset. A first counter, an adder for adding the least significant bit of the half-value data and the least significant bit of the reference data, and comparing the count value of the first counter with the output data of the adder, when the values match, A comparator for presetting a first counter, a first latch for holding a count value of the first counter when a rotation phase signal of the rotator arrives, and a first latch based on the reference data and a clock pulse. A speed error detecting means for calculating an error from a reference value of a repetition period of the rotation speed signal of the rotating body, and output data of the first latch and the speed error detecting means are combined. Driving means for driving the rotator by an error output signal obtained by the above-mentioned method, wherein the speed error detecting means multiplies reference data supplied from a memory means by a decimal number smaller than 1, and the multiplier And a second counter that counts clock pulses during one cycle of the rotation speed signal, and a second counter that holds difference data between the count amount of the second counter and the output data of the multiplier. And a servo device having a latch. 5. A memory means for storing reference data for generating a reference phase signal of a rotating body, and half-value data having a half size of the reference data supplied from said memory means inverting the sign. A first counter that is preset as a counter, an adder that adds the count value of the first counter and the least significant bit of the reference data, and compares the half-value data and the output data of the adder to determine A comparator for presetting the first counter when they coincide with each other;
A first latch that holds a count value of a counter of the above, speed error detection means that calculates an error from a reference value of a repetition period of a rotation speed signal of the rotating body based on the reference data and a clock pulse, A driving unit for driving the rotating body by an error output signal obtained by synthesizing output data of the first latch and the speed error detecting unit, wherein the speed error detecting unit is supplied from a memory unit. A multiplier for multiplying the reference data by a decimal number less than 1;
A second counter for counting clock pulses for one cycle of a rotation speed signal, wherein a data obtained by inverting the sign of the output data of the multiplier is preset; and a count amount of the second counter and output data of the multiplier. And a second latch for holding difference data from the second latch. 6. A memory means in which reference data for generating a reference phase signal of a rotating body is stored, and half-value data having a half size of reference data supplied from said memory means inverts logic. A first counter that is preset as a counter, an adder that adds the count value of the first counter and the least significant bit of the reference data, and compares the half-value data and the output data of the adder to determine A comparator for presetting the first counter when they coincide with each other;
A first latch that holds a count value of a counter of the above, speed error detection means that calculates an error from a reference value of a repetition period of a rotation speed signal of the rotating body based on the reference data and a clock pulse, A driving unit for driving the rotating body by an error output signal obtained by synthesizing output data of the first latch and the speed error detecting unit, wherein the speed error detecting unit is supplied from a memory unit. A multiplier for multiplying the reference data by a decimal number less than 1;
A second counter for counting clock pulses for one cycle of the rotation speed signal, wherein a data obtained by inverting the logic of the output data of the multiplier is preset; a count amount of the second counter and output data of the multiplier; And a second latch for holding difference data from the second latch. 7. A phase difference measuring means for outputting measurement data corresponding to a phase difference between a rotation phase signal of a rotating body and a reference phase signal as a count value of a clock pulse, and for generating a period of the reference phase signal. Memory means for supplying reference data to the phase difference measuring means; and a phase error by subtracting half the data of the reference data supplied from the memory means from output data of the phase difference measuring means. Phase error calculating means for calculating, a speed error detecting means for calculating an error from a reference value of a repetition period of the rotation speed signal of the rotating body based on the reference data and the clock pulse,
A driving unit for driving the rotating body by an error output signal obtained by combining output data of the phase error calculation unit and the speed error detection unit, the phase difference measurement unit includes a counter for counting clock pulses, An adder to which reference data supplied from the memory means is supplied as one input data, a register to supply output data of the adder as the other input data of the adder, A latch for holding a count value of the counter each time it arrives;
An arithmetic unit for calculating a difference between the output data of the register and the latch; and an ordering means for causing the adder to perform an addition operation after the operation timing of the latch, and thereafter, to fetch input data to the register. A servo device for outputting output data of the arithmetic unit as a deviation amount from a reference value of the phase signal. 8. A phase error calculation means for calculating measurement data according to a phase difference between a rotation phase signal of a rotating body and a reference phase signal as a count value of a clock pulse, and calculating a phase error based on the count value. A memory means for supplying reference data for generating a signal cycle to the phase error calculating means; and an error from a reference value of a repetition cycle of the rotation speed signal of the rotating body based on the reference data and a clock pulse. Speed error detecting means for calculating the phase error calculating means, and driving means for driving the rotating body by an error output signal obtained by combining output data of the phase error calculating means and the speed error detecting means, the phase error calculating means A counter for counting clock pulses, a first adder to which reference data supplied from the memory means is supplied as one input data, A register for supplying output data of the adder 1 as the other input data of the first adder; a latch for holding a count value of the counter each time the rotating body phase signal arrives; A second adder for adding half-value data having half the size of the reference data, an arithmetic unit for obtaining a difference between the second adder and the output data of the latch, and an operation timing of the latch. Later, the arithmetic unit is operated, subsequently, the first adder performs an addition operation, furthermore, the register is fetched input data, and then the second adder performs the addition operation. A servo means for outputting output data of the arithmetic unit as a phase error amount of the phase signal. 9. A speed error detecting means, comprising: a multiplier for multiplying reference data supplied from a memory means by a decimal number less than 1; a counter for counting clock pulses; and a counter for each time a rotating body speed signal arrives. And a register to which the latched data is transferred each time the speed signal arrives, and that the output of the multiplier is supplied as one input data and the output of the register is the other input. An adder supplied as data, an arithmetic unit for obtaining a difference between the adder and the output data of the latch, and operating the arithmetic unit after the operation timing of the latch and fetching input data into the register Sequence means for causing the adder to perform an adding operation thereafter, and outputting the output data of the arithmetic unit as a speed error amount. The servo apparatus according to claim 7 or 8 that.