JPH0478053A - Picture display permission signal generation circuit for video equipment - Google Patents

Abstract

PURPOSE:To display a picture immediately after a nearly stable phase locked state is attained by storing a phase-lock detection signal at prescribed periods, and generating a picture display permission signal when the storage bits of all shift registers show a phase-lock detection signal generating state. CONSTITUTION:The phase-lock detection circuit 10 of a cylinder control system, the phase-lock detection circuit 11 of a capstan control system, and the shift registers 13, 14 to receive phase-lock detection signals 24, 24a from these respectively are provided. Then, when a system is in the nearly perfect phase locked state, the lock detection signals 24, 24a are generated at every generation of each sample pulse 23, 23a, and when all the bits stored in each stage of each shift register 13, 14 become '1', and the stored bits of all the shift registers 13, 14 show the phase-lock detection signal generating state, the picture display permission signal is generated. Thus, the picture is displayed immediately after the nearly stable phase locked state is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a screen display permission signal generation circuit for video equipment, and more specifically, to a video tape recorder ( VT below
R), phase-locked #J detection that can detect phase-locked states of video movies, etc. at an early stage (related to improvement of the above circuit).

[Prior Art] In video equipment such as VTRs and video movies, motor control circuits for cylinder motors and capstan motors use phase control to control cylinder (or drum, or cylinder) rotation and tape running speed as desired. PLL control is performed using two feedback loops: 1 and speed control.

Images are displayed on the screen of video equipment only after the control systems for these cylinder motors and capstan motors are stable and the head can scan the track in the correct phase.

[Problem to be solved] Control system of cylinder motor and capstan motor or PLL
Since it is controlled, the time when the phase relationship between the head and track becomes phase locked due to the rotation of each motor is
It is almost constant from the time the power is turned on, and conventionally, a screen display permission signal is generated at a predetermined fixed timing from the time the power is turned on, in accordance with the time when this phase lock state is reached.
A stable image is displayed on the screen. However, if images are displayed at such timing, it takes time for the images to be displayed, which can be irritating to the viewer, so faster display is desired.

Therefore, it is possible to detect the phase lock state early and display the screen immediately, but in reality, the phase lock state is entered and released at the initial phase lock state, so it is simply It is not enough to simply detect the phase lock state, and there is a problem in that it is difficult to display a stable image.

The present invention is intended to solve the problems of the prior art, and aims to provide a screen display permission signal generation circuit for video equipment that can quickly start screen display from turning on the power. shall be.

[Means for Solving the Problems] The configuration of the screen display permission signal generation circuit for video equipment of the present invention that achieves the above object is as follows: A first shift register receives the signal from the capstan motor phase control system at a predetermined period, stores it as bit information, and shifts it in accordance with the period. Bit information of the first and second phase lock detection signals is stored in each stage of the second shift register, which is stored as information and shifted in accordance with the period, and the first and second soft registers. The device includes a detection circuit that detects the detection circuit, and a storage circuit that stores the detection signal from the detection circuit and generates a screen display permission signal in response to the detection signal.

[Operation] In this way, a shift register is provided corresponding to each of the cylinder motor control system and the capstan motor control system, and the phase lock detection signal is stored as a flag bit in each shift register at a predetermined period. Since the screen display permission signal is generated when all the shift register memory bits indicate the phase lock detection signal generation state, it is necessary to take sufficient timing before image permission is performed as in the conventional method. In addition, there is no unstable image display that occurs when simply detecting a phase lock state, and the screen is displayed immediately after entering a nearly stable phase lock state where the phase lock detection signal is detected multiple times in succession. It can be performed.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment in which the screen display permission signal generation circuit for video equipment of the present invention is applied to a VTR, and FIG. 2 is a timing chart for explaining its operation.

In FIG. 1, reference numeral 1 denotes a screen display permission signal generation circuit of a VTR, in which a phase counter 3 built in a phase control circuit 2 of a cylinder motor control system (hereinafter referred to as cylinder control system) receives trapezoidal wave section pulses 23 ( 2(d)) and a sample pulse 22 (see FIG. 2(C)) from the sample pulse generating circuit 4 of the cylinder control system. In addition, a trapezoidal wave section pulse 23a (see FIG. 2(d)) and a sample pulse for the capstan control system are generated from the phase counter 6 built in the phase control circuit 5 of the capstan motor control system (hereinafter referred to as the capstan control system). Sample pulse 22 from circuit 7
a (see FIG. 2(C)).

The screen display permission signal generation circuit 1 periodically receives signals corresponding to each other from the cylinder control system and the capstan control system. Corresponding signals of the stun control system will be indicated by the same number followed by "a", and their explanation will be omitted.

The phase counter 3 is, for example, a 10-bit counter, receives a reference phase signal 20 serving as a phase reference shown in FIG. 2(a), and starts counting at the rising edge of the reference phase signal 20.

The count state of this value is shown as an analog voltage value in the figure (b), which becomes a trapezoidal waveform 21 having a ramp voltage characteristic that increases linearly from zero volts to the power supply voltage VCC. The same applies to the phase counter 6 of the capstan control system, and its waveform is shown in parentheses as 21a in accordance with FIG. 3(b).

The trapezoidal wave interval pulses 23, 23a shown in FIG. 2(d) are as follows:
As shown by the dotted line, the phase counter 3 whose pulse width shows a phase lock state with respect to this trapezoidal waveform 21 (21a);
The pulse width is set to match the count value range of 6. This pulse width may span the entire sloped portion of the trapezoid.

The sample pulse generation circuit 4 generates a speed pulse (FGm) from the cylinder motor at a frequency corresponding to its rotational speed.
pulse) and its phase pulse (PGm pulse), a pulse which is synchronized with the FGm pulse, in phase with the PGm pulse, and has the same period as the trapezoidal wave section pulse 23 is generated as a sample pulse. Here, this pulse is generated in synchronization with the rising timing of the signal received from the VFF generating circuit 8 which generates a pulse signal with twice the period (30 Hz) of the city direct synchronization signal. The sample pulse generated in this manner is the sample pulse 22 shown in FIG. 2(C).

The sample pulse generation circuit 7 also generates a speed pulse (FG
c pulse) and its phase pulse (PGc pulse), a similar pulse is received from the control signal generating circuit 9 corresponding to the VFF generating circuit 8, and its rising edge is 30.
Sample pulse 22a as shown in FIG. 2(C) in Hz
occurs.

These sample pulses 22.22a,! : The generation circuit 1 receives the trapezoidal wave section pulse 23 and 23a and generates a phase lock detection circuit 10 for the cylinder control system, a phase lock detection signal 11 for the capstan control system, and a phase lock detection signal 11 for the capstan control system. 7-stage stars 13 and 14 with a 4-stage configuration (4 bits) each receiving a lock detection signal, ANI
) circuits 15a, 15b.

15c, NOR circuit 16a, and NOR circuit 16b.

OR circuit 16c1 and flip-flop (F/F) 1
It consists of 7, Furi 1. Generate screen display permission number 4M to Pflo and P17.

The phase lock detection circuits 10 and 11 each consist of an AND gate, and the output thereof is connected to the soft register 13.
．． 14 is input to the first stage. This circuit has a sample pulse 22 (22a) and a trapezoidal wave section pulse 23 (23).
a) is detected and the trapezoidal wave section pulse 23 (23a) becomes HI.
Sample 23 (2
3a), a lock detection signal 24 (24a) shown in FIG. 2(e) is generated.

The shift registers 13 and 14 receive the lock detection signal 2.
When 4.24a is occurring, the first stage receives an "H" output from the phase lock detection circuit 10.11 and stores "1" as bit information. Further, when the lock detection signal 24, 24a is not generated, bit information of "0" is stored in the first stage of each of the shift registers 13 and 14 in response to a LOW level (hereinafter referred to as "Lo") output. The information "1" and "00" stored in the first stage are sequentially shifted to the next stage each time a sample pulse 23, 23a occurs.

As a result, when the phase is almost completely locked, a lock detection signal is generated every time each sample pulse 23, 23a occurs, and each shift register 13,
The bits stored in each of the four stages of 14 are all "1".

The output of each stage of the shift register 13 of the cylinder motor control system is input to the AND circuit 15a, and the output of each stage of the shift register 14 of the capstan motor control system is input to the AND circuit 15a.
These shift registers 13, 1
When all the bits in each stage of 4 become “1”, AND
Circuit 15a.

A N I) circuit 15 (・or “H”) receiving the output of 15b
In other words, both the /linda control system and the capstan control system enter the phase lock state, which sets the stored information in the four stages of shift registers 13 and 14 to "1", respectively. A when following the degree
ND circuits 15a, 15b+15c detect that the phase lock state is entered.

This means that since each of the shift registers 13 and 14 has a four-stage configuration, the phase lock detection period continues for four periods of the sample pulse. This state is
This occurs when the phase lock state becomes almost stable after entering the phase lock state. If the phase lock is not detected even once by the sample signal 23.23a in either the cylinder control system or the capstan control system before all the storage bits of the shift register 13.14 become "1", in other words, if the phase lock is not detected even once by the sample signal 23.23a, If the lock detection state is unstable or the sample period does not last for 4 cycles,
- When it is released even at - degree, the AND circuit 15c
No phase lock state detection signal is generated at the output.

The phase lock state detection signal generated in the AND circuit 15c is applied to the D terminal of the flip-flop 17 and stored in the flip-flop 17.

Then, the Q output of the flip-flop 17 is outputted from the output terminal -i'-18 as a screen display permission signal.

As a result, when a phase lock state detection signal is generated, even if one value in each stage of the shift registers 13 and 14 changes to "0" due to noise etc., it will not affect the detection of the phase lock state. The screen display permission signal continues to occur. This allows stable image display.

Here, the data stored in the flip-flop 17 indicating that both the cylinder control system and the capstan control system have entered the phase lock state is stored in the NOR circuits lea, 16b, and O.
Reset by R circuit 16c.

will be played. The NOR circuits lea and 16b each receive the output of each stage of the shift register 13 and 14, and the OR circuit 1
6c receives the outputs of NOR circuits 16a and 16b. Therefore, when all bits stored in each stage of the shift register in either the cylinder motor control system or the capstan motor control system are "O", a reset signal is generated from the OR circuit 18c. As a result, flip-flop 1
The data set in step 7 is set in the initial state when the power is turned on or when the phase lock state of either the cylinder motor control system or the capstan motor control system is released for a relatively long period of time. In such a case, even if the screen is displayed, only a distorted image will be obtained, so the screen display permission signal should be canceled.

In this way, by using a four-stage shift register, the phase lock state is fixed to some extent, and the screen display permission signal can be generated immediately in a stable state. Moreover, this screen display permission signal is issued almost immediately after both the cylinder control system and capstan control system enter the phase lock state and become stable, so there is sufficient time for each to stabilize as in the conventional case. To generate a screen display permission signal in a short time without securing time, and to display an image immediately.

As explained hereafter, in the embodiment, the soft register 13
．． Is the number of stages in 14 a four-stage configuration? This can be determined depending on the characteristics of the phase control circuit of the video equipment.
It is only necessary that a plurality of stages of shift registers be provided in both the seven-ring control system and the capstan control system.

In the embodiment, the sample pulse for sampling the trapezoidal pulse is generated from a signal of a predetermined frequency that is synchronized with the FG pulse and matched with the phase of the PG, or is generated from a signal of a predetermined frequency that is synchronized with the PG pulse and at least the phase of the PG pulse. It is sufficient that the phase matches the pulse and the pulse has a period that is the same as the period of the phase counter or an integral multiple thereof. Furthermore, the present invention is not limited to phase lock detection using sample pulses as described above, and it is also possible to obtain phase lock signals at a predetermined period from each phase control circuit of the cylinder motor control system and the capstan motor control system. You can use that if you like. In such a case, it is sufficient to receive the phase lock signal at a predetermined period, and the number of stages in the shift register is determined in relation to the period in which the phase lock signal is obtained, and the lock is activated when the phase lock state is almost completed. It is sufficient to generate a state detection signal.

[Effects of the Invention] As can be understood from the explanation in 1- below, in this invention, a shift register is provided corresponding to each of the cylinder motor control system and the capstan motor control system, and a shift register is provided for each of the 7-foot registers. The phase lock detection signal is stored as a flag bit at a predetermined period, and the memory bit of all soft recorders is stored.

Since the screen display permission signal is generated when the phase lock detection signal is generated, the screen display permission signal is generated immediately after entering the almost stable phase lock state where the phase lock detection signal is generated several times in succession. can be displayed on the screen.

As a result, it is possible to realize a video device that can display a screen with a quick start at the same time as the power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment in which the screen display permission signal generation circuit for video equipment of the present invention is applied to a VTR, and FIG. 2 is a timing chart for explaining its operation. DESCRIPTION OF SYMBOLS 1... Screen display permission signal generation circuit, 2... Phase control circuit of cylinder control system, 3, 6... Phase counter, 3
a, 7a... Trapezoidal wave interval pulse, 4... Sample pulse generation circuit of cylinder control system, 4
a, 7a... sample pulse, 5... phase control circuit of capstan control system.

Claims (1)

[Claims] (1) A first shift register that receives a first phase lock detection signal from the cylinder motor phase control system at a predetermined cycle, stores it as bit information, and shifts the capstan motor phase in accordance with the cycle; a second shift register that receives a second phase lock detection signal from a control system at a predetermined period, stores it as bit information, and shifts it in accordance with the period; and each of the first and second shift registers. a detection circuit for detecting that the bit information of the first and second phase lock detection signals is stored in the step; a detection signal from the detection circuit is stored; and a screen display permission signal is generated in accordance with the detection signal. 1. A screen display permission signal generation circuit for video equipment, comprising a memory circuit for generating a screen display permission signal.