JP3719509B2 - シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 - Google Patents
シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 Download PDFInfo
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- JP3719509B2 JP3719509B2 JP2002099202A JP2002099202A JP3719509B2 JP 3719509 B2 JP3719509 B2 JP 3719509B2 JP 2002099202 A JP2002099202 A JP 2002099202A JP 2002099202 A JP2002099202 A JP 2002099202A JP 3719509 B2 JP3719509 B2 JP 3719509B2
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- latch circuit
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3875—Pipelining a single stage, e.g. superpipelining
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Multi Processors (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002099202A JP3719509B2 (ja) | 2002-04-01 | 2002-04-01 | シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 |
| EP03006757A EP1351134A3 (en) | 2002-04-01 | 2003-03-25 | Superpipelined arithmetic-logic unit with feedback |
| US10/404,182 US7171535B2 (en) | 2002-04-01 | 2003-04-01 | Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002099202A JP3719509B2 (ja) | 2002-04-01 | 2002-04-01 | シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003296096A JP2003296096A (ja) | 2003-10-17 |
| JP2003296096A5 JP2003296096A5 (2) | 2005-04-07 |
| JP3719509B2 true JP3719509B2 (ja) | 2005-11-24 |
Family
ID=28035903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002099202A Expired - Fee Related JP3719509B2 (ja) | 2002-04-01 | 2002-04-01 | シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7171535B2 (2) |
| EP (1) | EP1351134A3 (2) |
| JP (1) | JP3719509B2 (2) |
Families Citing this family (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1669868A4 (en) * | 2003-09-30 | 2009-03-25 | Sanyo Electric Co | PROCESSOR AND INTEGRATED CIRCUIT WITH CONVERTIBLE CIRCUIT AND PROCESSING PROCESS THEREFORE |
| JP4478050B2 (ja) * | 2005-03-18 | 2010-06-09 | 株式会社リコー | Simd型マイクロプロセッサ及びデータ処理方法 |
| JP2006287675A (ja) * | 2005-04-01 | 2006-10-19 | Renesas Technology Corp | 半導体集積回路 |
| US7681017B2 (en) * | 2005-11-01 | 2010-03-16 | Lsi Corporation | Pseudo pipeline and pseudo pipelined SDRAM controller |
| US8024394B2 (en) * | 2006-02-06 | 2011-09-20 | Via Technologies, Inc. | Dual mode floating point multiply accumulate unit |
| US20070226455A1 (en) * | 2006-03-13 | 2007-09-27 | Cooke Laurence H | Variable clocked heterogeneous serial array processor |
| US8656143B2 (en) | 2006-03-13 | 2014-02-18 | Laurence H. Cooke | Variable clocked heterogeneous serial array processor |
| JP2007249843A (ja) * | 2006-03-17 | 2007-09-27 | Fujitsu Ltd | 再構成可能な演算装置 |
| US8327115B2 (en) | 2006-04-12 | 2012-12-04 | Soft Machines, Inc. | Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode |
| US7870556B2 (en) * | 2006-05-16 | 2011-01-11 | Ab Initio Technology Llc | Managing computing resources in graph-based computations |
| US8346831B1 (en) * | 2006-07-25 | 2013-01-01 | Vivante Corporation | Systems and methods for computing mathematical functions |
| US20080052429A1 (en) * | 2006-08-28 | 2008-02-28 | Tableau, Llc | Off-board computational resources |
| US20080052490A1 (en) * | 2006-08-28 | 2008-02-28 | Tableau, Llc | Computational resource array |
| US20080126472A1 (en) * | 2006-08-28 | 2008-05-29 | Tableau, Llc | Computer communication |
| US20080052525A1 (en) * | 2006-08-28 | 2008-02-28 | Tableau, Llc | Password recovery |
| WO2008061154A2 (en) | 2006-11-14 | 2008-05-22 | Soft Machines, Inc. | Apparatus and method for processing instructions in a multi-threaded architecture using context switching |
| DE212007000102U1 (de) * | 2007-09-11 | 2010-03-18 | Core Logic, Inc. | Rekonfigurierbarer Array-Prozessor für Gleitkomma-Operationen |
| US9152427B2 (en) | 2008-10-15 | 2015-10-06 | Hyperion Core, Inc. | Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file |
| JP5590849B2 (ja) * | 2009-10-08 | 2014-09-17 | キヤノン株式会社 | 複数の処理モジュールを有する並列処理回路を備えるデータ処理装置、その制御装置、およびその制御方法、プログラム |
| CN103250131B (zh) | 2010-09-17 | 2015-12-16 | 索夫特机械公司 | 包括用于早期远分支预测的影子缓存的单周期多分支预测 |
| KR101966712B1 (ko) | 2011-03-25 | 2019-04-09 | 인텔 코포레이션 | 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트 |
| WO2012135031A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines |
| CN103562866B (zh) | 2011-03-25 | 2018-03-30 | 英特尔公司 | 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段 |
| EP2710481B1 (en) | 2011-05-20 | 2021-02-17 | Intel Corporation | Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines |
| WO2012162189A1 (en) | 2011-05-20 | 2012-11-29 | Soft Machines, Inc. | An interconnect structure to support the execution of instruction sequences by a plurality of engines |
| IN2014CN03678A (2) | 2011-11-22 | 2015-09-25 | Soft Machines Inc | |
| WO2013077876A1 (en) | 2011-11-22 | 2013-05-30 | Soft Machines, Inc. | A microprocessor accelerated code optimizer |
| US9891924B2 (en) | 2013-03-15 | 2018-02-13 | Intel Corporation | Method for implementing a reduced size register view data structure in a microprocessor |
| US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
| US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
| EP2972836B1 (en) | 2013-03-15 | 2022-11-09 | Intel Corporation | A method for emulating a guest centralized flag architecture by using a native distributed flag architecture |
| WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
| WO2014150971A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for dependency broadcasting through a block organized source view data structure |
| WO2014151018A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for executing multithreaded instructions grouped onto blocks |
| US9886279B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Method for populating and instruction view data structure by using register template snapshots |
| US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
| WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
| US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
| US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
| US9747104B2 (en) * | 2014-05-12 | 2017-08-29 | Qualcomm Incorporated | Utilizing pipeline registers as intermediate storage |
| JP2017174291A (ja) | 2016-03-25 | 2017-09-28 | ルネサスエレクトロニクス株式会社 | 画像処理装置、画像処理方法、及び自動車制御装置 |
| US11340875B2 (en) * | 2020-06-02 | 2022-05-24 | Sri International | Searchable storage of sequential application programs |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179734A (en) * | 1984-03-02 | 1993-01-12 | Texas Instruments Incorporated | Threaded interpretive data processor |
| JPH0767063B2 (ja) * | 1990-01-23 | 1995-07-19 | ヤマハ株式会社 | デジタル信号処理回路 |
| US5038311A (en) * | 1990-08-10 | 1991-08-06 | General Electric Company | Pipelined fast fourier transform processor |
| JP3096387B2 (ja) * | 1994-01-28 | 2000-10-10 | 三菱電機株式会社 | 数値演算処理装置 |
| JPH08137819A (ja) * | 1994-11-04 | 1996-05-31 | Hitachi Ltd | 接続制御装置 |
| US6044166A (en) * | 1995-01-17 | 2000-03-28 | Sarnoff Corporation | Parallel-pipelined image processing system |
| JPH10240558A (ja) * | 1997-02-24 | 1998-09-11 | Hitachi Ltd | データ処理装置の制御方法、データ処理装置、電子線描画装置 |
-
2002
- 2002-04-01 JP JP2002099202A patent/JP3719509B2/ja not_active Expired - Fee Related
-
2003
- 2003-03-25 EP EP03006757A patent/EP1351134A3/en not_active Withdrawn
- 2003-04-01 US US10/404,182 patent/US7171535B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1351134A3 (en) | 2007-11-07 |
| US7171535B2 (en) | 2007-01-30 |
| US20030200237A1 (en) | 2003-10-23 |
| JP2003296096A (ja) | 2003-10-17 |
| EP1351134A2 (en) | 2003-10-08 |
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