JP2003296096A5 - - Google Patents

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Publication number
JP2003296096A5
JP2003296096A5 JP2002099202A JP2002099202A JP2003296096A5 JP 2003296096 A5 JP2003296096 A5 JP 2003296096A5 JP 2002099202 A JP2002099202 A JP 2002099202A JP 2002099202 A JP2002099202 A JP 2002099202A JP 2003296096 A5 JP2003296096 A5 JP 2003296096A5
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Japan
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data
latch circuit
instructions
input
salc
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JP2002099202A
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Japanese (ja)
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JP3719509B2 (ja
JP2003296096A (ja
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Priority to JP2002099202A priority Critical patent/JP3719509B2/ja
Priority claimed from JP2002099202A external-priority patent/JP3719509B2/ja
Priority to EP03006757A priority patent/EP1351134A3/en
Priority to US10/404,182 priority patent/US7171535B2/en
Publication of JP2003296096A publication Critical patent/JP2003296096A/ja
Publication of JP2003296096A5 publication Critical patent/JP2003296096A5/ja
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Publication of JP3719509B2 publication Critical patent/JP3719509B2/ja
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JP2002099202A 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法 Expired - Fee Related JP3719509B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002099202A JP3719509B2 (ja) 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法
EP03006757A EP1351134A3 (en) 2002-04-01 2003-03-25 Superpipelined arithmetic-logic unit with feedback
US10/404,182 US7171535B2 (en) 2002-04-01 2003-04-01 Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002099202A JP3719509B2 (ja) 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法

Publications (3)

Publication Number Publication Date
JP2003296096A JP2003296096A (ja) 2003-10-17
JP2003296096A5 true JP2003296096A5 (2) 2005-04-07
JP3719509B2 JP3719509B2 (ja) 2005-11-24

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JP2002099202A Expired - Fee Related JP3719509B2 (ja) 2002-04-01 2002-04-01 シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法

Country Status (3)

Country Link
US (1) US7171535B2 (2)
EP (1) EP1351134A3 (2)
JP (1) JP3719509B2 (2)

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KR102083390B1 (ko) 2013-03-15 2020-03-02 인텔 코포레이션 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
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