JPH01102794A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To stably and surely perform a sense amplifier operation and fast readout of data by providing a constant voltage circuit so as to keep the potential of a sense amplifier driving signal line which transmits a signal to activate the sense amplifier constant at the time of reading out the data in a memory cell. CONSTITUTION:The title device is constituted so that the constant voltage circuits 100 are provided at the sense amplifier driving signal lines 14 and 17 to activate the sense amplifiers 18 and 19, respectively, and the potential of the sense amplifier driving signal lines 14 and 17 can be kept constant until the sense amplifiers 18 and 19 are activated after information in the memory cell 1 is read out. Therefore, no rising or the lowering of the potential occurs at the sense amplifier driving signal lines 14 and 17 according to the charge/ discharge of the potential of bit lines 2 and 7, and a large potential difference between the bit lines 2 and 7 can be obtained sufficiently, thereby, the operating allowance of the sense amplifiers 18 and 19 can be heightened. In such a way, it is possible to stabilize the operation of the sense amplifier and also, to accelerate the operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] 5 This invention relates to a dynamic random access memory (
Regarding sense amplifier circuits used in DRAM), etc.
In particular, it relates to speeding up the operation of the sense amplifier circuit.

[Prior Art] FIG. 4 is a circuit diagram showing the configuration of a portion of a conventional dynamic random access memory. Normally, dynamic random access memory (hereinafter referred to as DRAM) is
It has a memory cell array arranged in a matrix consisting of a plurality of rows and columns, and FIG. 4 shows the main parts related to one column of this memory matrix.

In FIG. 4, a pair of bit lines 2 and 7 have a folded bit line configuration, and mutually complementary data Bn.

iπ is transmitted. A memory cell 1 for storing 1-bit data is arranged at the intersection of a word line 3 and a bit line 2, which select one row of the memory cell matrix. word line 3
is a word line selection signal Rn for selecting a word line.
is transmitted. The memory cell 1 is connected to a capacitor 6 that stores memory cell data in the form of charges through a node 4, and is configured to select a memory cell in response to a word line selection signal Rn transmitted to a word line 3. Capacity 6 to bit line 2
The transistor is composed of an n-channel insulated gate field effect transistor (hereinafter abbreviated as MOS transistor) connected to the transistor. The other end of memory cell capacitor 6 is connected to a ground line. Bit line pair 2 is connected to one end of bit line pair 2゜7.
．． A balancing transistor 12 is provided to keep the potentials of the bit line pair 2.7 at the same potential during a standby state (from the end of one memory cycle to the start of the next memory cycle). The plain commercial transistor 12 has a signal line 13 connected to its gate.
It receives an equilibration signal φE via. Also, bit line 2.
7 is an n-channel MOS) transistor 9 for charging.
．． 10, it is connected to a power supply line 8 to which a constant potential of Vcc/2 is supplied. The charging transistors 9 and 10 are
It turns on in response to the charging signal φP applied via the terminal 11, and the bit line 2.7 enters the memory cell standby state.
are charged to a potential of Vcc/2, respectively. Here, Vcc indicates the operating power supply voltage of the memory device.

A sense amplifier is provided at the other end of the bit line pair 2.7 to detect and amplify the signal voltage of the bit line pair 2.7. The sense amplifier is a cross-coupled p-channel MOS
It consists of transistors 15 and 16 and cross-coupled n-channel MOS transistors 18 and 19. One electrode of the p-channel transistor 15, 16 is connected to the clock signal line 14, and the clock signal line 1
Bit line pair 2.7 is activated in response to a clock signal (first sense amplifier activation signal φ,) transmitted to bit line pair 2.7.
Among them, the higher potential bit line potential is charged to a higher potential.

The other electrodes of n-channel MOS transistors 15 and 16 are connected to bit lines 2 and 7, respectively. The other end of the clock signal line 14 is connected between the first constant voltage source terminal 22 and the clock signal line 14 in order to provide the activation timing of the sense amplifier, and is responsive to the sense amplifier drive signals φ and P. A first sense amplifier driving transistor (n-channel MOS transistor) 23 is provided, which is turned on at a certain time and charges the clock signal line 14 to the power supply voltage Vcc level. The first sense amplifier drive signal φ, P is terminal 2
5, the first sense amplifier driving transistor 23
is applied to the gate electrode.

One electrodes of the n-channel MOS transistors 18 and 19 are both connected to a signal line 17 to which a clock signal φ is supplied, and the other electrodes are respectively connected to a bit line 2.7'. At the other end of the clock signal line 17, in order to provide timing for activating the sense amplifier, a second sense amplifier drive signal φ5M turns on in response to the second sense amplifier drive signal φ5M and discharges the clock signal line 17 to the ground potential. Sense amplifier driving transistor (n-channel MOS transistor) 24
is provided. ``The second sense amplifier driving transistor 24 has one end connected to the second clock signal line 17, the other electrode connected to the ground potential, and its gate electrode connected to the second sense amplifier through the terminal 26. Receives amplifier drive signal φg"M. MOS transistors 15, 16.1
8 and 19 constitute a sense amplifier circuit consisting of a flip-flop circuit. Here, the bit lines 2 and 7 each have a parasitic capacitance 27.28, the first clock signal line 14 has a parasitic capacitance ff120, and the second clock signal line 17 has a parasitic capacitance 21. do.

FIG. 5 shows the logic “1” (“H”) of the DRAM shown in FIG.
FIG.

The operation of the conventional DRAM will be described below with reference to FIGS. 4 and 5. In order to explain the read operation of memory cell 1, it is necessary to explain the operation from the previous cycle, so the operation waveform diagram for the previous cycle is also shown in FIG. There is. Now, the case where memory cell 1 is selected will be explained.゛As shown in FIG. 5, in the previous cycle, a large amount of data was read from either memory cell connected to bit line 2 or 7, so the potential of bit line 2 became Ov1.
Assume that the bit line 7 potential is at Vcc level. This state of the bit line potential is just an example, and the opposite state also exists. The word line (not shown) that is currently in this state and has selected one of the memory cells mentioned above.
The potential becomes Ov, and one memory cycle ends.

At time to, the sense amplifier drive signal φ.

P, φ, and N begin to rise and fall, respectively, MOS transistors 23 and 24 become non-conductive, and the sense amplifier is inactivated.

At time t1, when the bit line balancing signal φE starts to rise, the balancing transistor 12 becomes conductive.

As a result, charges move from the bit line 7 with a high potential to the bit line 2 with a low potential, and the voltages of the bit lines 2.7 are both balanced to V c c /2. When the bit line potential becomes V c c /2, the sense amplifier drive signal lines 14 and 17 become conductive, and charges are transferred from the sense amplifier drive signal line 14 with the higher potential to the sense amplifier drive signal line 17 with the lower potential. The sense amplifier drive signal line 14 potential is equal to the bit line precharge voltage V c c
/ 2, the absolute value of the threshold voltage vTH of the MOS transistor 15.16 is higher than the voltage V c c /
2 +IVTHPI, and on the other hand, the potential of the sense amplifier drive signal line 17 is a potential Vcc/2 lower than the bit line precharge potential (equilibrium potential) Vcc/2 by the threshold voltage VT)IN of the MOS transistors 18 and 19. 2-V
v, IN.

At time t2, the potential of the bit line 2.7 is set to Vc c
/ 2, the clock signal (charging signal) φP starts to rise from Ov, and as a result, the MOS transistors (charging transistors) 9 and 10 become conductive, and the power supply line having the potential of Vcc/2 bit line 2 to 8
．． 7 is connected.

At time t3, the charging clock signal φP stops rising, thereby ending the operation of the previous cycle. This completes one memory cycle and enters a standby state.

At time t4, in order to finish the balancing and charging of the bit line 2.7 and start the next cycle, that is, the current cycle, the bit line balancing signal φE and the charging signal φP start to fall, and the MoS transistor 9.10 and 12 become non-conductive.

At time t5, when the word line 3 is selected by a decoder means (not shown) and the word line selection signal Rn rises, the MOS transistor 5 of the memory cell 1 becomes conductive, and the charge accumulated in the memory cell capacitor 6 is transferred to the bit line. 2, and the potential of bit line 2 begins to rise. This change in the potential of the bit line 2 causes the Mo8 transistor 19 of the sense amplifier to conduct, thereby changing the potentials of the bit line 7 and the sense amplifier drive signal line 14,17. This bit line 7. Details of the potential changes of the sense amplifier drive signal lines 14 and 17 will be described later. The potential change of bit line 2 is slight (equation 1
00 mV) and typically has a time constant of a few Ions.

At time t6, the sense amplifier drive signal φ.

P1φgN are lowered and raised, respectively, to generate sense amplifier activation signals φ6. φ is activated to drive the sense amplifier and amplify the minute signal appearing on the bit line 2.7. In order to operate the sense amplifier stably, it is preferable to increase the potential difference between its input signals, that is, the bit lines 2.7 as much as possible. For this purpose, it is necessary to take a long time between time t5 and time t6, but in order to increase the successive speed, the time between time t5 and time t6 is generally set to 15 nS to 25 nS.

At time t7, when the amplification by the sense amplifier ends, the potentials of the bit lines 2.7 each reach VCC%OV, and become complete logic "1" and "0" levels. The potential appearing on bit line 2.7 is read out through a readout section (column selection transistor and data line) not shown.

Next, a minute voltage change that appears on the bit line 2.7 after the word line drive signal Rn rises when reading information held in a memory cell will be described in detail with reference to the drawings.

FIG. 6 is a waveform diagram showing in detail the potential changes appearing on each bit line and sense amplifier drive signal line when the word line potential rises, from time t4 to time t6 in FIG.
It is a figure which shows the state change between. That is, the operating waveform diagram in FIG. 6 shows the state before the sense amplifier becomes active.

Now, let us consider the case where data of logic "1" is read from memory cell 1 in the same manner as in the explanation of the second series. Word line drive signal Rn
rises and its level is Vcc/2 +VT H
When the voltage exceeds N (VTHN is the threshold voltage of an n-channel MOS transistor), MOS transistor 5 of memory cell 1 begins to conduct, and bit line 2 and node 4 are connected. As a result, the charge held in the memory cell capacitor 6 begins to move from the node 4 toward the bit line 2, and the potential of the bit line 2 begins to rise. Here, in the above description and the following description, all n-channel MOS transistors have the same threshold voltage VT)IN, and all p-channel MOS transistors also have the same threshold voltage V).
It is assumed that it has THP.

This rise in the potential of bit line 2 causes the MO of the sense amplifier to
The S transistor 19 begins to conduct, charges move from the bit line 7 toward the sense amplifier drive signal line 17, and the potential of the sense amplifier drive signal line 17 increases while the potential of the bit line 7 decreases. Due to this potential drop in the bit line 7, the Mo3) transistor 15 begins to conduct.
Charge moves from the sense amplifier drive signal line 14 toward the bit line 2, and the potential of the bit line 2 increases. When this phenomenon is repeated, it is thought that the potential of the bit line 2 gradually increases, but in reality, the capacitance value of the parasitic capacitance 21 attached to the sense amplifier drive signal line 17 increases Since it is smaller than the parasitic capacitance 28, the potential of the sense amplifier drive signal line 17 rises faster, which makes it difficult for the MOS transistor 19 to conduct, so the potential rise of the bit line 2 stops at a relatively small value. .

This phenomenon is a transient phenomenon, and detailed analysis requires calculations for this transient phenomenon, but here, for the purpose of a rough comparison with the present invention, we will explain the final state in which charge movement has stopped. This will be explained with reference to FIG.

FIG. 7 is a diagram showing the charge movement path and the potential after the potential change in each signal line.

Now, the potential changes of the bit lines 2 and 7 and the sense amplifier drive signal lines 14 and 17 after the charge movement are ΔV+ΔV2, respectively.
It is assumed that Δv7, AV14, and ΔV17. Here, ΔV is the amount of potential change associated with reading logic "1#" data from memory cell 1.
The capacitance values of C20, C21, C27 and C2 are respectively
8.

First, considering the movement of charge between the bit line 2 and the sense amplifier drive signal line 14, according to the law of conservation of charge, (Vcc/2+ΔV)-C27 + (VCC/2+1VT11 P +) ・C2
O-(Vcc/2+ΔV+ΔV2)-C27+ (Vc
c/2+! VT HP l-ΔV14) - Therefore, C27-AV2-C20-AV14 (1) is obtained. Similarly, bit line 7 and sense amplifier drive signal line 17
Even between C28-AV7-C21-AV17 (2).

Furthermore, since the MoS transistor 19 becomes non-conductive and the movement of charge to the sense amplifier drive signal line 17 is stopped, Vc C/2+ΔV+ΔV, 2-Vv HN-mVcc
/2-VT HN+ΔV17, that is, Δv+Δv2-AV17-, <3>. Similarly, since the MOS transistor 15 becomes non-conductive and the movement of charge to the bit line 2 is stopped, V c c / 2−ΔV7+ l VT 11 P
1-Vc c/2+ l VT 11 P +-Δ
V14, that is, ΔV7−ΔV14−(4). Substituting the above equation (4) into equation (2), C28-
ΔV14−C21−AV17·(5).

According to equation (1), ΔV14- (C27/C20) -ΔV2・ (
6). Substituting equation (6) into equation (5) yields (C2
7-C28/C20)-AV2 -C21-ΔV17 That is, ΔV17- (C27・C28/C20・C21)・Δ
V2 − ...(7) Substituting equation (7) into equation (3) gives ΔV-1(C27・C28/C20・C21)−1)
・ΔV2, that is, AV2-AV/l (C27-C28/C20-C2
1)-11...(8) Similarly, ΔV7-IV14-ΔV/ ((C28/C21)-(
C20/C27)1...(9) ΔV17- (C28/C21)-ΔV14-AV/
il, -(C20-C21/C27-C28))
...(10) is obtained. Here, (C27-C2g): (C20-021)zlO:
l.

ΔVz200mV Then, ΔV2-200/9942mV.

ΔV7-ΔV14=1.1x'200-220mΔV1
7- (100/99) ・200-202V is obtained. From the above values, the input potential difference Vs of the sense amplifier is: Vs-V2-V7 (11)-Vcc/2
+ΔV+ΔV2-(Vcc/2-ΔV7) Zen ΔV+Δv2+Δv7 -200+2+220 Exposure 422mV.

[Problems to be Solved by the Invention] The value of the input potential difference Vs of the sense amplifier described above is the value when the time between time t5 and time t6 shown in FIG. 5 is taken as infinite, and in reality, Since this time is set to a relatively short finite value for high-speed reading, the input potential difference Vs of the sense amplifier actually becomes a value smaller than the above-mentioned value. Furthermore, due to voltage noise components due to capacitive coupling between adjacent bit lines, and electrical imbalance between bit lines that occurs incidentally during the actual memory device manufacturing process, the potential difference between bit lines is 1/3 of the above value. ~1/4 (14
0 to 105 mV), the input potential difference of the sense amplifier becomes a small value, and there is a problem that the operating margin of the sense amplifier becomes small.

Therefore, an object of the present invention is to eliminate the drawbacks of the conventional semiconductor memory device as described above, increase the potential difference between a pair of bit lines in a relatively short time, and stabilize the operation of a sense amplifier. An object of the present invention is to provide a semiconductor memory device that can be operated at high speed.

[Means for Solving the Problems] A semiconductor memory device according to the present invention provides a constant voltage circuit for each sense amplifier drive signal line for activating a sense amplifier, and reads out memory cell information onto a bit line. The potential of the sense amplifier drive signal line is kept constant until the subsequent sense amplifier is activated.

[Function] In the semiconductor memory device according to the present invention, each of the sense amplifier drive signal lines is provided with a constant voltage circuit, and the drive signal lines are kept at a constant voltage until just before the sense amplifier becomes active after reading memory cell information. Therefore, the potential of each sense amplifier drive signal line does not rise or fall due to charging and discharging of the bit line potential, and the discharge from the low potential bit line to the sense amplifier drive signal line via the sense amplifier does not occur. Since charging from the sense amplifier drive signal line via the sense amplifier to the high-potential bit line is sufficiently performed without stopping midway, the potential difference between the bit line pair can be made sufficiently large. The human power potential difference with respect to the amplifier can be increased to a large value, and the operating margin of the sense amplifier can be increased.

[Embodiment of the Invention] FIG. 1 is a diagram showing the main parts of a semiconductor memory device that is an embodiment of the present invention. In FIG. 1, the same or corresponding parts as in FIG. is attached.

In FIG. 1, as a feature of the present invention, when reading memory cell data, sense amplifier drive signal lines 14 and 17
A constant voltage circuit 100 is provided to keep the potential constant. The constant voltage circuit 100 has a sense amplifier drive signal line 14
It has a part for keeping the potential of the sense amplifier drive signal line 17 constant, and a part for keeping the sense amplifier drive signal line 17 at a constant potential.

The part for keeping the sense amplifier drive signal 14 at a constant potential is connected to the power supply voltage Vcc via the terminal 22 at one electrode (
The n-channel MOS transistor 29 is connected to the gate of the n-channel MOS transistor 29, and the other electrode (source) is connected to the first sense amplifier drive signal line 14. A stabilizing capacitor 30 for stabilizing the gate potential of the MOS transistor 29 and a constant voltage applying section for applying a predetermined constant potential to the gate electrode of the MOS transistor 29 are provided.

Similarly, the part for keeping the potential of the second sense amplifier drive signal line 17 constant has its -edge 5 (drain) connected to the ground potential, and the other electrode (source) connected to the sense amplifier drive signal line. a stabilizing capacitor 38 connected to the gate of the p-channel MOS transistor 36 for stabilizing the gate potential of the MOS transistor 36;
It has a constant voltage applying section for applying a predetermined potential to the gate of the OS transistor 36.

A constant voltage applying section for applying a predetermined potential to the gates of each of the transistors 29 and 36 (MOS) is used in common for both transistors, and one end thereof is connected to the power supply voltage V c, c via the power supply terminal 22 . an n-channel MOS transistor 33 whose gate and drain are connected to the other end of the resistor 32; and an n-channel MOS transistor 33 whose source is connected to the source of the n-channel MOS transistor 33 via a node 34; An n-channel MOS transistor 35 whose drain is connected to the node 43, and a p-channel MOS transistor whose gate and drain are connected to the node 43)
An n-channel MOS connected to the gate and drain of transistor 35 and whose source is connected to node 41
transistor 42 and its source connected to n via node 41
connected to the source of the channel MOS transistor 42;
Consisting of an n-channel MOS transistor 40 whose gate and drain are connected to each other, and a resistor 39 whose other end is connected to the gate and drain of the p-channel MOS transistor 40 and whose lower end is connected to ground potential. be done. The other end of the resistor 32 is connected to M through the node 31.
Connected to the gate electrode of OS transistor 29. The other end of the resistor 39 is connected to the MOS transistor 3 via the node 37.
It is connected to the gate electrode of No. 6. The MOS transistor included in the constant voltage circuit 100 has a threshold voltage similar to that of the MOS transistor included in the sense amplifier. That is, each n-channel MOS transistor has a threshold voltage Vmin, and each p-channel MOS transistor has a threshold voltage v, Hr. Further, the resistance values of the resistors 32 and 39 have a large value of several tens to several hundreds of Ω, and are set to be equal to each other.

Furthermore, the conduction resistances of n-channel MOS transistors 33 and 42 are set equal and low. Similarly, the conduction resistances of the p-channel MOS lunges 35 and 40 are set equal and low. In this circuit configuration, the components are vertically symmetrically arranged with respect to the node 43. Therefore, the potential at node 43 is half of the power supply potential VcC, that is, V c c
It will be kept at a potential of /2.

FIG. 2 is a diagram showing potential changes in each signal line during reading of memory cell data in a semiconductor memory device according to an embodiment of the third invention, and corresponds to FIG. 6. In the state shown in FIG. 2, the memory cell 1 connected to the word line 3 and the bit line 2 has information of logic "1", and the potential when this memory cell 1 is connected to the bit line 2 Changes are indicated. The operation of a semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

As mentioned above, the resistance values of the resistors 32 and 39 are set to be equal and high (several tens to hundreds of ohms), and n
The conduction resistance values of the channel MOS transistors 33 and 42 are equal to each other, and the p-channel MOS transistor 35
．． The conduction resistance values of 40 are also set equal to each other, and the respective conduction resistance values are set low. Therefore, the potential of the node 43 is V, which is between the potential of the power supply terminal 22 and the ground wire.
It becomes cc/2.

Further, since each of the MOS transistors 33, 35, 42, and 40 has a diode-connected configuration in which its drain and gate are connected, a forward voltage drop corresponding to its threshold voltage is given. Therefore, the first
A circuit part for keeping the sense amplifier drive signal line 14 at a constant potential, that is, Mo3) transistors 29.3B, 35
, the resistor 32, and the capacitor 30, the potentials of each part of the circuit section are as follows.

Node 34: Potential of node 43 + MO3) Threshold voltage of transistor 35 MVCC/2+ l VT 11 P l s Node 3
1: Potential of node 34 + Threshold voltage of MOS transistor 33 - VCC/2+lVTMF l+VT11N% Sense amplifier drive signal line 14: Potential of node 31 - Threshold voltage of MOS transistor 29 -Vc c/2+ l Vv
11 P l (11) Here, the reason why the MOS transistor 29 performs the function described in 1. is because it is connected in a so-called source follower configuration. This state (the state of equation (11)) means that the MoS transistor 29 is placed in a boundary state between a conductive state and a non-conductive state. That is, if the potential force of the sense amplifier drive signal line 14 is V c c / 2+ l VT
) When the voltage is about to fall below l P +, the MOS transistor 29 becomes conductive, moves the charge from the power supply terminal 22, and increases the potential of the sense amplifier drive signal line 14.
Maintain a constant value of Vc c/2+ I Vv HP l. Conversely, when the potential of the sense amplifier drive signal line 14 becomes higher than this potential, the Mo5) transistor 29 becomes non-conductive. - Similarly, the circuit consisting of Mo5) transistor 36.40°42, resistor 39, and capacitor 38 performs the function of keeping the potential of the sense amplifier drive signal line 17 at a constant potential of VCC/2 VT,N. In this circuit portion, the MOS transistor 36 is placed at the boundary between a conductive state and a non-conductive state. Therefore, if the potential of the sense amplifier drive signal line 17 is about to rise above Vcc/2-VT Hu, the MOS transistor 36 becomes conductive,
The electric charge on the sense amplifier drive signal line 17 is discharged to the ground potential, and the potential on the sense amplifier drive signal line 17 decreases, whereby the potential on the sense amplifier drive signal line 17 becomes Vc c/2.
−Vy HN is kept at a constant value.

When the potential of the sense amplifier drive signal line 17 falls, the MOS transistor 36 becomes non-conductive.

Under the above-mentioned conditions, the change in potential of the bit line 2.7 before activation of the sense amplifier when data of logic "1m" is read from the memory cell 1 as in the conventional semiconductor memory device will be explained. .

When one word line 3 is selected by the output of a decoder (not shown), the word line drive signal Rn rises, and when its potential level exceeds Vcc/2+VdHN, the Mo8) transistor 5 with memory cell>1/1 is activated. It begins to conduct, and the charge stored in the memory cell capacitor 6 of the memory cell 1 is transmitted onto the bit line 2, thereby increasing the potential of the bit 12.

In response to this rise in the potential of the bit line 2, the M'OS transistor 19 constituting the sense amplifier starts conducting, and charges move from the bit line 7 toward the sense amplifier drive signal line 17. Since this charge flows to the ground potential through the MOS transistor 36, the sense amplifier drive signal line 17
The potential of is kept at a constant value (Vc C/2-VTHN). Therefore, since the MOS transistor 19 does not become non-conductive, the charge continues to move from the bit line 7, and the potential of the bit line 7 continues to decrease. On the other hand, as the potential of the bit line 7 decreases, the MOS transistor 15 becomes conductive, charges move from the sense amplifier drive signal line 14 toward the bit line 2, and the potential of the bit line 2 increases.

At this time, when the electric charge moves in the sense amplifier drive signal line 14 and its potential starts to drop, the two MOS transistors become conductive and the electric charge is supplied from the power supply via the power supply terminal 22, so that the sense amplifier is driven. The potential of the signal line 14 is kept at a constant value (Vcc/2+IVrHpl). As a result, the MOS transistor 15 does not become non-conductive, so the charge continues to move from the sense amplifier drive signal line 14, and the potential of the bit line 2 continues to rise. This increase in the potential of bit line 2 and decrease in the potential of bit line 7 function as positive feedback, and the potential difference between bit lines 2 and 7 increases, and eventually the potential of bit line 2 increases to the sense amplifier drive signal line 1.
4, that is, VCC/2+1VT11F+, the potential of the bit line 7 is the potential of the sense amplifier drive signal line 17,
That is, it becomes stable when it reaches Vcc/2-Vt)IN.

Normally MO3) transistor threshold voltage VT'HN,
! VT HP I Eta, 6V~0.8
Vl: Since this is set, the potential difference between the bit lines in the conventional semiconductor memory device can be greatly widened in the present invention, as is clear from a comparison between FIG. 6 and FIG. 2. Therefore, the sense amplification operation of the potential difference between the bit lines due to the next activation of the sense amplifier can be performed stably.

Furthermore, when performing a sense amplification operation at the same potential difference as in a conventional semiconductor memory device, the time required to reach that potential difference is significantly shortened compared to a conventional semiconductor memory device, so the point at which the sense amplification operation starts is can be made faster than in conventional devices, making it possible to read data at high speed.

In addition, in the configuration of the embodiment shown in FIG.
To simplify the explanation, so-called dummy cells have been omitted. However, as shown in FIG. 3, two dummy word lines 52 and 55 are provided, a dummy cell 54 is arranged at the intersection of bit line 2 and dummy word 155, and a dummy cell 54 is arranged at the intersection of dummy word line 52 and bit line 7. If the dummy cell 51 is provided in the structure, the effects of the present invention can be further enhanced. That is, in the so-called dummy cell configuration, for example, when reading information held in the memory cell 1 in the configuration shown in FIG. 1, if the word line drive signal Rn on the word line 3 rises from OV to Vcc,
Word line 3 and bit line 2 are capacitively coupled due to the parasitic capacitance ff150 between word line 3 and bit line 2 (this is caused by the crossing of word line 3 and bit line 2), and the potential of bit line 2 is slightly MO3! of memory cell 1 is placed on the bit line 7 side. - A dummy MOS transistor 51 having the same shape as the transistor 5 is provided, a dummy word line 52 is connected to the gate electrode of this MOS transistor 51, and a signal DRn similar to the word line 3 is connected to the dummy word line 52.
(At this time, the signal R is supplied to the dummy word line 55.
This is a method of canceling capacitive coupling noise by applying the same coupling voltage to the bit line 2 side through the parasitic capacitance 53 to the bit line 7 side (a signal DRn complementary to n is given).

Therefore, if a dummy cell as shown in FIG. 3 is provided in the configuration of the present invention, even more stable sense amplification operation can be performed. Further, a dummy cell is provided on the bit line 2 side as well as on the bit line 7 side.

In the above embodiment, the data read operation was explained when the memory cell 1 has information of logic "1", but this also applies when the memory cell 1 has information of logic "0". Even in that case, the present invention can obtain the same effect as the above embodiment.

[Effects of the Invention] As described above, according to the present invention, a constant voltage circuit is provided to keep the sense amplifier drive signal line potential, which transmits a signal for activating the sense amplifier, constant during memory cell data reading. Therefore, when reading memory cell data, the bit line potential is sufficiently charged and discharged to each sense amplifier drive signal line through the transistors that constitute the sense amplifier, and the potential difference between the bit line pair is sufficiently increased. This allows the potential difference of the input signal during sense amplifier operation to be a large value, increasing the operating margin of the sense amplifier.
It becomes possible to perform stable and reliable sense amplification operation and high-speed data reading.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the main parts of a semiconductor memory device which is an embodiment of the present invention. FIG. 2 is a waveform diagram showing potential changes in each signal line when reading data from a memory cell of a semiconductor memory device according to an embodiment of the present invention. Third
The figure is a diagram showing the configuration of a semiconductor memory device according to another embodiment of the present invention, and is a diagram showing the configuration when dummy cells are provided. FIG. 4 is a diagram showing the configuration of a conventional semiconductor memory device, and is a diagram showing the circuit configuration of the main part associated with a pair of bit lines. FIG. 5 is a diagram showing operating waveforms during detection and amplification of memory cell data in a conventional semiconductor memory device. FIG. 6 is a diagram showing in more detail potential changes on each signal line during memory cell data reading (until immediately before sense amplification operation) in a conventional semiconductor memory device. FIG. 7 is a diagram showing the potential of each signal line and the direction of charge flow when the potential change in the sense amplifier drive signal line and the sense amplifier is stable in a conventional semiconductor memory device. In the figure, 1 is a memory cell, 2 and 7 are bit lines, 3 is a word line, 5 is a MOS transistor forming the memory cell, 6 is a memory cell capacitor forming the memory cell,
9 and 10 are charging transistors, 12 is a balancing transistor, 14 is a first sense amplifier drive signal line, 15.1
6 is a p-channel MO8) transistor constituting a sense amplifier; 17 is a second sense amplifier drive signal line; 18, 1
9 is an n-channel MOS transistor that constitutes a sense amplifier, and 29.33.42 is an n-channel M for maintaining constant voltage.
OS transistor, 35.36.40 is a p-channel MOS transistor for constant voltage maintenance, 32.39 is a resistor, 1
00 is a constant voltage circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (11)

[Claims] (1) A plurality of bit lines in which two bit lines are arranged in pairs, and a plurality of bit lines are provided for each of the bit line pairs, and one of the bit line pairs is provided in response to a first activation signal. a first sense amplifier made of a first conductivity type transistor that charges a high potential bit line to a higher potential; and a first sense amplifier provided for each of the bit line pairs and activated in response to a second activation signal. A semiconductor memory device comprising a second sense amplifier comprising a second conductivity type transistor that discharges a low potential bit line of the bit line pair to a lower potential, the bit line being precharged to a predetermined potential. is provided for a first signal line that transmits the first activation signal, and the first activation signal is transmitted to the first signal line and the first sense amplifier is activated. a first potential holding means for holding the first signal line potential at a potential equal to the sum of the precharge potential and the absolute value of the threshold voltage of the first conductivity type transistor until immediately before the first signal line potential is changed; provided for a second signal line that transmits the second activation signal, and until just before the second activation signal is transmitted to the second signal line and the second sense amplifier is activated. comprising a second potential holding means for holding the second signal line potential at a potential equal to the difference between the absolute value of the precharge potential and the threshold voltage of the second conductivity type transistor;
Semiconductor storage device. (2) The semiconductor memory device according to claim 1, wherein the second sense amplifier includes two cross-coupled first conductivity type insulated gate field effect transistors. (3) The semiconductor memory device according to claim 1, wherein the second sense amplifier includes two second conductivity type insulated gate field effect transistors that are cross-coupled. (4) The first potential holding means includes a first transistor of a second conductivity type connected in the form of a source follower between a first constant voltage source and the first signal line; 2. The semiconductor memory device according to claim 1, further comprising: first constant voltage generating means coupled to one constant voltage source and applying a predetermined potential to the control electrode of the first transistor. (5) The first constant voltage generating means includes a first resistor whose one end is connected to the first constant voltage source, and a diode connected to the other end of the first resistor. The patent includes a series body of a second conductivity type second transistor and a first conductivity type third transistor connected to each other, and a control electrode of the first transistor is connected to the other end of the resistor. A semiconductor memory device according to claim 4. (6) The second potential holding means includes: a fourth transistor of the first conductivity type connected in the form of a source follower between the second signal line and the second constant voltage source; and second constant potential generating means for applying a predetermined potential to the control electrodes of the four transistors.
The semiconductor storage device described in 1. (7) The second constant voltage generating means includes a second resistor whose one end is connected to the second constant voltage source, and a diode connected to the other end of the second resistor. Claim 6, comprising a series body of a first conductivity type transistor and a second conductivity type transistor connected to each other, the other end of the second low antibody being connected to the control electrode of the fourth transistor. The semiconductor storage device described in 1. (8) The first and second constant potential generation means are configured to calculate the sum of the precharge potential and the sum or difference of the absolute values of the respective threshold voltages of the first conductivity type transistor and the second conductivity type transistor. A semiconductor memory device according to any one of claims 5 to 7, which generates a potential consisting of: (9) The first constant voltage generating means and the second constant voltage generating means are connected in series between the first constant voltage source and the second constant voltage source. The semiconductor memory device according to any one of items 5 to 7. (10) The first conductivity type transistor is a p-channel insulated gate field effect transistor, and the second conductivity type transistor is an n-channel insulated gate field effect transistor. The semiconductor memory device according to any one of the above. (11) Each of the bit lines includes a dummy cell connected to the bit line so as to provide a reference potential during operation of the first and second sense amplifiers.
The semiconductor storage device described in 1.