JPH0217874B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a randomly readable and writable random access memory (RAM).

Recently, the number of static RAMs whose internal components operate dynamically has been gradually increasing. This is for the purpose of reducing current consumption or improving operating speed by performing dynamic operation. Also,
Even if it is not a dynamic operation, many integrated circuits generate clock pulse signals within the integrated circuit to initialize or precharge internal nodes of the integrated circuit. This is also done for the purpose mentioned above.

The above clock pulse signals or signals for dynamic operation are generated in synchronization with the chip enable signal (a signal for putting the chip into operation) that is input to the integrated circuit, or in synchronization with changes in the memory address signal. I also make them. Due to the clock pulse signal generated in this manner, the current associated with charging and discharging for initializing the circuit flows as an instantaneous peak current during operation. Generally, as the memory capacity increases, the stray capacitance associated with the main signal lines increases, so these charging and discharging currents naturally increase. Furthermore, as the operating speed of the memory becomes faster, the charging and discharging of these stray capacitances must be performed faster, and therefore the charging and discharging currents also have sharper peaks. The instantaneous peak current during this operation significantly increases the high-frequency component of fluctuations in the power supply potential, generates noise due to induced potential in input signals or various signal lines within the memory chip, and adversely affects the operating margin of the circuit. Not only this, but also the difficulty of mounting technology increases.

For example, in a memory system that detects a change in an address signal and generates a clock pulse signal to control an internal circuit in synchronization with the change, charging and discharging the internal circuit by this clock signal causes a power supply as described above. A failure mode occurred in which noise was introduced into the line, and this noise caused a clock pulse signal to be generated again, causing the circuit to oscillate.

Furthermore, as described above, the instantaneous peak current becomes larger when a large stray capacitance is charged and discharged in a short period of time. In a semiconductor memory, places where this large stray capacitance exists are row lines, bit lines, and the like. Conventionally, all of the bit lines were precharged at the same time, so the instantaneous peak current for precharging this bit line was extremely large compared to charging and discharging other internal nodes.

FIG. 1 shows a general circuit of a semiconductor memory that performs such dynamic operation. In this memory, a memory cell 1 driven by a selected row line SL outputs its stored information to a pair of bit lines Qn, n. The pair of data output to the bit lines Qn, n have opposite phases to each other, and the sense amplifier 2 detects and outputs this data. Furthermore, before the row line SL is selected, the precharge circuit 3 normally selects the bit line.
Qn,n are precharged to a predetermined potential level.

A conventional circuit of the precharge circuit 3 is shown in FIG. In the figure, MOS transistors T ₁ and T ₂ are connected in parallel between the power supply Vcc and the bit line Qn.
The gate of transistor _T1 is connected to the power supply Vcc,
At the gate of transistor T ₂ there is a precharge signal
PC is entered. In addition, MOS transistor T ₃ ,
_T4 is connected in parallel between the power supply Vcc and the bit line n, and the gate of the transistor _T4 is connected to the power supply Vcc.
The signal PC is input to the gate of the transistor _T3 . In addition, two bit lines
A MOS transistor _T5 whose gate receives the signal PC is connected between Qn and n. Here, transistors T ₁ and T ₄ act as load transistors of memory cell 1, and transistors T 2 and T ₄ act as load transistors of memory cell 1.
_T3 is connected from the power supply Vcc to the bit line Qn by the signal PC.
The transistor _T5 acts as a pre-charge transistor to charge the bit line.
It works to equalize the potentials of Qn and n.

In the precharge circuit configured as described above, as shown in the waveform diagram of Fig. 3, before the row line SL is selected and becomes the "1" level, the precharge signal PC becomes the "1" level and the bit is set to the "1" level. Line Qn,
Precharge for Qn is started. In other words, when the precharge signal PC becomes "1" level, transistors T ₂ and T ₃ become conductive, and the bit line
Qn,n is charged. At this time, bit line n
is charged until it reaches the same potential as the bit line Qn, and this charging current appears as a peak current. Therefore, a large instantaneous peak current flows when charging the bit line capacitance, which becomes relatively large as the memory capacity increases, which becomes a noise source and adversely affects the operating margin of the circuit.

The present invention was made in view of the above circumstances, and
A precharge circuit that charges a pair of bit lines for transferring data to and from a memory cell shorts the pair of bit lines when the power supply is at a predetermined voltage or higher, and shorts the pair of bit lines when the power supply is at a predetermined voltage or lower. By short-circuiting and pre-charging with the power supply, the instantaneous peak current during memory access operation is suppressed and current consumption is reduced.
It is an object of the present invention to provide a semiconductor memory that can increase the circuit operation margin and increase the operation speed.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows a precharge circuit for a semiconductor memory as described above with reference to FIG.

The circuit consists of a power supply Vcc and a pair of bit lines Qn,n
and a MOS transistor T ₆ whose gate is supplied with a second precharge signal PC2,
T ₇ are connected respectively, and the above bit line
The first precharge signal is applied to the gate between Qn and n.
The configuration is such that a MOS transistor _T8 to which PC1 is input is connected. In this case, when the power supply Vcc is above a predetermined potential, the second precharge signal PC2 is at the "0" level, and when the power supply Vcc is below the predetermined potential, the second precharge signal PC2 is the same signal as the first precharge signal PC1. Note that the first precharge signal PC1 is a signal similar to the precharge signal PC shown in FIG. 2 described above.

The operation of the precharge circuit having the above configuration will be explained with reference to the signal waveform diagram of FIG. In FIG. 5, the solid line indicates when the power supply Vcc is higher than the predetermined voltage,
The dotted line indicates when the power supply Vcc falls below a predetermined voltage. The first signal before a new row line SL is selected
PC1 becomes the "1" level. At this time, transistor _T8 becomes conductive, and bit lines Qn and n become at the same potential. In other words, if the bit line Qn is at the "1" level and the bit line n is at the "0" level, the charge on the bit line Qn moves to the bit line Qn through the transistor _T8 , so that both bit lines Qn,
Qn has the same potential. At this time, the bit lines n have the same potential. At this time, bit line n is charged by the charge on bit line Qn, and the power supply Vcc has nothing to do with it. Therefore, no large instantaneous peak current flows when charging the bit line.

However, simply shorting the bit lines Qn and n as described above causes a problem when the potential of the power supply Vcc drops. In other words, at this time, for example, the bit line
Since the "1" level of QnN decreases in accordance with the power supply Vcc potential, the potential after shorting the bit lines Qn,n may be too low and become out of the sensitivity of the sense amplifier 2, or the potential of the bit lines Qn,n may be low. Because it's too much,
When reading data from the memory cell 1, there is a risk that the data in the memory cell 1 will be inverted, that is, written from "0" to "1". In other words,
If only the first precharge signal PC1 is used, a problem arises in that the power supply margin becomes small.

On the other hand, when the power supply Vcc becomes lower than the predetermined potential, the first
At the same time as the second precharge signal PC1, the second precharge signal PC2 also becomes "1" level. The voltage waveform at this time is shown by the dotted line in FIG. That is, the operation at this time is approximately the same as the case shown in FIG. 3 described above, but the charging potential difference becomes smaller as the power supply Vcc is lowered, and the instantaneous peak current also decreases accordingly. The charging/discharging current I in this case is calculated by the following formula.

I=ΔV・C/Δt (1) Here, C is the capacity to be charged, ΔV is the potential difference to be charged, and Δt is the time required for charging. In other words, from the above equation (1), it can be seen that the smaller the potential difference ΔV, the smaller the charging current I. i.e. power supply
When Vcc is high, the bit line _is
By short-circuiting Qn and n, the electric charge stored in one bit line charges the other bit line, and the instantaneous peak current flowing from the power supply is reduced to almost zero. However, when the power supply Vcc becomes low, the transistor _T8 At the same time, transistors T ₆ and T ₇ are also made conductive. However, the potential difference ΔV to be charged at this time
is also smaller because the power supply Vcc is lower, and the instantaneous peak current is also smaller accordingly. Therefore, the semiconductor memory of the above embodiment has the advantage that the power supply margin is wide and the instantaneous peak current is small.

FIG. 6 shows a precharge circuit according to another embodiment of the invention. This precharge circuit is
This is a modification of the circuit shown in FIG. 4 described above, and load MOS transistors T ₉ , whose gates are connected to the power supply Vcc, are connected between the power supply Vcc and the bit lines Qn, n, respectively.
_T10 is connected, and the other parts are the same as in Fig. 4. Of course, the transistors T ₉ and T ₁₀ may be of any type as long as they can serve as a load; for example, they may be simple resistors. Even with this precharge circuit,
If the conduction resistance of the transistors T ₉ and T ₁₀ is sufficiently large, there is no effect on the instantaneous peak current, and therefore the same effect as that of the embodiment described above is achieved.

In the above embodiment, the first and second precharge signals PC1 and PC2 are set to "0" before a new row line SL is selected, but the selection of the row line SL and the precharge signal "0" It goes without saying that 1" levels may overlap.

FIG. 7 shows a circuit for generating the first precharge signal PC1 used in the semiconductor memory of the present invention. This circuit consists of depletion type MOS transistors T ₁₁ , T ₁₃ , T ₁₅ and enhancement type MOS transistors connected between the power supply Vcc and ground, respectively.
MOS transistors T ₁₂ , T ₁₄ , and T ₁₆ constitute a buffer circuit B ₁ with two stages of inverters I ₁ and I ₂ , respectively, and the output terminal of the first stage inverter I ₁ is connected to the transistor T of the second stage inverter I ₂ . ₁₄ and the gate of the transistor T ₁₆ of the buffer circuit B ₁ respectively. Then, the output terminal of the second stage inverter _I2 is connected to the gate of the transistor T15 of the buffer circuit _B1 , and the transistor of this buffer circuit _B1 is connected to the gate of the transistor _T15 of the buffer circuit B1.
One end of a capacitor C is connected to the output ends of T ₁₅ and T ₁₆ , and the other end is connected to a precharge clock pulse φ _PC via a MOS transistor T ₁₇ whose gate is connected to the power supply Vcc. By applying this clock pulse φ _PC to the gate of the transistor T ₁₂ of the first stage inverter I ₁ , the first precharge signal PC 1 is obtained from the output terminal of the transistor T ₁₇ .

In the above circuit, when the precharge clock pulse φ _PC reaches the "1" level, the other side of the capacitor C is charged via the transistor _T17 , so that the potential level of the signal PC1 line rises. At this time, since the transistor T ₁₂ of the first stage inverter I ₁ is turned on, the transistors T ₁₄ and T ₁₆ are turned off, and one side of the capacitor C becomes the "1" level. Moreover, at this time, since the signal PC1 line has already been charged to a certain potential, the signal PC1 is raised to a potential higher than the power supply Vcc due to the capacitive coupling of the capacitor C. Therefore, the bit line Qn,n
Charging and discharging will be carried out quickly.

FIG. 8 shows a circuit for generating the second precharge signal PC2 used in the semiconductor memory of the present invention. This circuit consists of depletion type MOS transistors T ₁₈ , T ₂₀ , T ₂₂ , T ₂₄ , T ₂₆ and enhancement type MOS transistors T ₁₉ , T ₂₁ , T ₂₃ , connected in series between power supply Vcc and ground, respectively.
T ₂₅ and T ₂₇ each constitute a 5-stage circuit including 4-stage inverters I ₁ to I ₄ and a buffer circuit B ₁ . Furthermore, the gate of the first stage inverter _I1 is connected to the power supply Vcc
Resistor R ₁ of the voltage divider circuit provided between and earth,
The output terminal of the third stage inverter I3 is connected to the mutual connection point a of _R2 , and the output terminal of the third stage inverter _I3 is grounded through the MOS transistor _T28 , whose gate is applied with the inverted precharge clock pulse _PC , and the final stage buffer circuit B. The configuration is such that it is connected to the gate of transistor _T26 of _{No. 1} . And the first stage inverter I ₁
A predetermined voltage signal from the voltage divider circuit is input to the gate of transistor T ₁₉ , and at the same time, the gate of transistor T ₂₈
An inverted clock pulse _PC is input to the gate of the buffer circuit _B1 to obtain a second precharge signal PC2 from the output stage of the final stage buffer circuit B1.

In the above circuit, the second precharge signal PC2 is generated when the power supply Vcc becomes lower than a predetermined potential. That is, now the resistance R ₁ is 40KΩ,
If the resistance R ₂ is 10KΩ, the potential at the connection point a is
It becomes 0.2Vcc. Therefore, if the threshold voltage of the inverter _I1 is set to 0.8V, if the power supply Vcc is 4V or more, the potential at point a will be 0.8V or more, and if the power supply Vcc is 4V or less, the potential at point a will be 0.8V or less. For this reason,
The output of the inverter _I1 becomes a "0" level if the power supply Vcc is 4V or more, and becomes a "1" level if it is less than 4V.

Therefore, if the power supply Vcc is 4V or higher, the output of inverter _I2 will be at the "1" level, and the output of inverter _I3 will be at the "0" level.In the end, the output of inverter _I3 will be at the "0" level regardless of the clock pulse φ _PC . Therefore, the second precharge signal PC2 becomes "0" level. Conversely, if the power supply Vcc falls below 4V,
The output of inverter I ₁ is “1” level, the inverter
The output of _I2 becomes "0" level, and the output of inverter _I3 changes from "1" to "0" of the inverted clock pulse _PC .
The second precharge signal goes to "1" level in synchronization with the change in , and goes to "1" level in synchronization with this.
Transistors T ₆ and T ₇ of the precharge circuits of FIGS. 4 and 6 described above are driven by PC2. In addition, inverter I ₄ buffer circuit B ₁ in Figure 8
It goes without saying that the circuit shown in FIG. 7 may be used instead.

In the semiconductor memory of the present invention, the signal generation circuits shown in FIGS. Since the precharge circuit shown in FIG. 4 or FIG. 6 is driven, the instantaneous peak current when charging the bit lines Qn, n can be suppressed.

As explained above, according to the present invention, the precharge circuit that charges the pair of bit lines for transferring data to and from the memory cell shorts the pair of bit lines when the power supply voltage exceeds a predetermined voltage, and the power supply When the voltage is below a predetermined voltage, the pair of bit lines are short-circuited and pre-charged by the power supply, thereby suppressing the instantaneous peak current during memory access operation and reducing current consumption.
A semiconductor memory that can increase the circuit operation margin and improve the operation speed can be provided.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram showing an example of RAM, Figure 2 is a circuit configuration diagram showing an example of RAM.
The figure is a detailed circuit diagram of the precharge circuit in Figure 1,
3 is a waveform diagram for explaining the circuit operation of FIG. 2, FIG. 4 is a circuit diagram showing a precharge circuit of a semiconductor memory according to an embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining the circuit operation of FIG. 4. FIG. 6 is a circuit diagram showing a precharge circuit of a semiconductor memory according to another embodiment of the present invention, and FIGS. 7 and 8 are waveform diagrams for explaining the circuits of FIGS. 4 and 6, respectively. FIG. 2 is a circuit diagram showing a driving signal generation circuit. 1...Memory cell, 2...Sense amplifier, 3...Precharge circuit, SL...row line, Qn, n...bit line, PC1, PC2...precharge signal, _T1 to _T27
…transistor, Vcc…power supply.

Claims (1)

[Claims] 1. A plurality of memory cells that store data, a row line that selects and drives a memory cell at a predetermined location from the plurality of memory cells, and a pair that receives a pair of data from the memory cell. conduction control of the bit line and the transistor provided between the pair of bit lines, and transmits the charge on the high potential side of the pair of bit lines to the low potential side, thereby changing the potential of the pair of bit lines when reading data. and pre-charging means for pre-charging the bit line to a potential between the bit lines and the memory cell so that a steady current does not flow from the power supply terminal through the bit line and the memory cell after the pre-charging is completed. 1. A semiconductor memory characterized in that the semiconductor memory is processed only by 2. The semiconductor memory according to claim 1, wherein the precharge means includes a transistor provided between the bit lines and a precharge signal for controlling conduction of the transistor. 3 a plurality of memory cells for storing data, a row line for selecting and driving a memory cell at a predetermined location from among the plurality of memory cells, and a pair of bit lines for receiving a pair of data from the memory cells; A load element provided between the bit line and the power supply, a transistor provided between the pair of bit lines, and a pulse signal generated by detecting an address change control the conduction of the transistor, thereby controlling the conduction of the transistor. and a precharging means for transmitting the charge on the high potential side of the line to the low potential side and precharging it to a potential between the potentials of the pair of bit lines when reading data, and after the precharging is completed, the bit line and the bit line are transferred from the power supply terminal. A semiconductor memory characterized in that the charge level of the bit line is maintained only by the memory cell so that no steady current flows through the memory cell. 4 A plurality of memory cells that store data, a row line that selects and drives a memory cell at a predetermined location from these memory cells, a pair of bit lines that receive a pair of data from the memory cell, and a power source. a precharge circuit that short-circuits the pair of bit lines when the voltage of the bit line is above a predetermined value, shorts the pair of bit lines when the voltage of the power supply is below a predetermined value, and precharges the pair of bit lines by the power supply; A semiconductor memory characterized by suppressing instantaneous peak current during memory access operation. 5. The precharge circuit includes a first transistor connected between the pair of bit lines and operated by a first precharge signal to bring the pair of bit lines to the same potential, and a transistor between the power supply and the pair of bit lines. A second and a third bit line are connected to each other and operate in response to the second precharge signal to precharge the pair of bit lines.
5. The semiconductor memory according to claim 4, further comprising a transistor. 6. The precharge circuit is connected between a first transistor connected between the pair of bit lines and operated by a first precharge signal to bring the pair of bit lines to the same potential, and the power supply and the pair of bit lines. second and third transistors connected to the second precharge signal and operating in response to a second precharge signal to precharge the pair of bit lines; and second and third transistors connected between the power supply and the pair of bit lines, respectively. 5. The semiconductor memory according to claim 4, further comprising fourth and fifth load transistors connected in parallel. 7. The semiconductor memory according to claim 5 or 6, wherein the second precharge signal is generated before the memory cell is selected by the row line.