JPH01102952U - - Google Patents

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Publication number
JPH01102952U
JPH01102952U JP20123687U JP20123687U JPH01102952U JP H01102952 U JPH01102952 U JP H01102952U JP 20123687 U JP20123687 U JP 20123687U JP 20123687 U JP20123687 U JP 20123687U JP H01102952 U JPH01102952 U JP H01102952U
Authority
JP
Japan
Prior art keywords
clock pulse
storage
storage element
pulse
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20123687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20123687U priority Critical patent/JPH01102952U/ja
Publication of JPH01102952U publication Critical patent/JPH01102952U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示したブロツク図
、第2図は第1図に示した実施例のバツクアツプ
を示した回路図、第3図は第1図に示したシフト
レジスタの内部構成図、第4図は第1図に示した
クロツクパルス発生回路から送出されるそれぞれ
のクロツクパルスを示した説明図、第5図は第1
図に示したシフトレジスタの他の構成例を示した
回路図、第6図は本考案の他の実施例を示したブ
ロツク図、第7図は従来例を示したブロツク図、
第8図は第7図に示した記憶部の内部構成図、第
9図は第7図に示した記憶部の他の構成例を示し
た回路図である。 5a,5b…記憶ブロツク、7a,7b…シフ
トレジスタ、19…クロツクパルス発生回路。
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a backup of the embodiment shown in Fig. 1, and Fig. 3 is an internal diagram of the shift register shown in Fig. 1. 4 is an explanatory diagram showing each clock pulse sent out from the clock pulse generation circuit shown in FIG. 1, and FIG.
6 is a block diagram showing another embodiment of the present invention, FIG. 7 is a block diagram showing a conventional example,
FIG. 8 is an internal configuration diagram of the storage section shown in FIG. 7, and FIG. 9 is a circuit diagram showing another example of the configuration of the storage section shown in FIG. 7. 5a, 5b...memory block, 7a, 7b...shift register, 19...clock pulse generation circuit.

Claims (1)

【実用新案登録請求の範囲】 所定のパルス周期を有する第1のクロツクパル
スと、この第1のクロツクパルスより長いパルス
周期を有する第2のクロツクパルスとを送出する
クロツクパルス送出手段と、 配列される複数の記憶素子に記憶されるデータ
を、前記第1のクロツクパルスに同期して当該各
記憶素子に後続する記憶素子へ順次シフトする第
1の記憶手段と、 この第1の記憶手段から送出され、かつ配列さ
れる複数の記憶素子に順次記憶されるデータを、
前記第2のクロツクパルスに同期して当該各記憶
素子に後続する記憶素子へ順次シフトする第2の
記憶手段と を有することを特徴とするデータ記憶装置。
[Claims for Utility Model Registration] Clock pulse sending means for sending out a first clock pulse having a predetermined pulse period and a second clock pulse having a longer pulse period than the first clock pulse; and a plurality of arranged memories. a first storage means for sequentially shifting data stored in the element to a storage element subsequent to each storage element in synchronization with the first clock pulse; and data sent from the first storage means and arranged in sequence. data stored sequentially in multiple storage elements,
A data storage device comprising: second storage means for sequentially shifting each storage element to a subsequent storage element in synchronization with the second clock pulse.
JP20123687U 1987-12-28 1987-12-28 Pending JPH01102952U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20123687U JPH01102952U (en) 1987-12-28 1987-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20123687U JPH01102952U (en) 1987-12-28 1987-12-28

Publications (1)

Publication Number Publication Date
JPH01102952U true JPH01102952U (en) 1989-07-12

Family

ID=31491606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20123687U Pending JPH01102952U (en) 1987-12-28 1987-12-28

Country Status (1)

Country Link
JP (1) JPH01102952U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6126182A (en) * 1984-07-17 1986-02-05 Fujitsu Ltd Data logger

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6126182A (en) * 1984-07-17 1986-02-05 Fujitsu Ltd Data logger

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