JPH01109763A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductor integrated circuit devices, particularly vertical mask RO
The present invention relates to a technique that is effective when applied to a semiconductor memory device having M (Read Only Memory).

[Conventional technology]

The semiconductor memory device having the mask It, OM is low cost,
Excellent security against information destruction. Mask ROMs include vertical (serial type) mask ROMs and horizontal (parallel type) mask ROMs. Vertical mask ROM is horizontal mask R
Compared to OM, it is easier to integrate (it has the feature of being able to increase the amount of information).
No. 8 describes a vertical mask ROM that is most suitable for high integration. In this vertical mask ROM, a plurality of first layer gate electrodes are arranged at predetermined intervals in the gate length direction, and a second layer gate electrode is formed between the first layer gate electrodes. The first layer gate electrode is made of a first layer polycrystalline silicon film, and constitutes a memory cell consisting of an MIS capacitor or MISFET. The second layer gate electrode is
The MI
S answer! Alternatively, a memory cell consisting of MISFET is configured. The memory cell connects the MI'S valley formed between the gate electrode and the substrate, or the channel region of the memory cell on both sides of the MIS capacitor as a current supply port (source) and current extraction port (drain). It can be said that it consists of MISFET. Each memory cell is therefore connected in series. There is no need to provide a semiconductor region corresponding to a source region or a drain region between the first layer gate electrode and the second layer gate electrode (between the memory cells). Therefore, the memory cell area can be significantly reduced.

[Problem that the invention seeks to solve]

The inventor of the present invention investigated writing information into memory cells in the above-mentioned vertical mask ROM and found that the following problem occurred.

Writing of information into the memory cell constituted by the second layer gate electrode is performed as follows. First, place the first
A layered gate electrode is formed. Thereafter, a first information writing impurity is introduced into the memory cell in which information is to be written, that is, the main surface of the substrate between the first layer gate electrodes, using the first layer gate electrode as a mask. The first information writing impurity is applied to the threshold voltage control region (channel region) under the region where the second layer gate electrode is to be formed, from the depression type to the enhancement type with a threshold 1 direct voltage. or vice versa. In writing the first information, the first layer gate electrode is used as a mask for impurity introduction, so
It can be formed in a self-aligned manner with respect to the first layer gate electrode.

On the other hand, writing of information into a memory cell constituted by the 2g first layer gate electrode is performed as follows. First, a second information writing impurity is introduced in advance into the main surface of the substrate below the region where the first layer gate electrode is to be formed. The second information writing impurity sets the threshold It voltage of the memory cell from a depression type to an enhancement type or vice versa. Thereafter, a first layer gate electrode is formed on the substrate into which the second information writing impurity has been introduced. Therefore, the region into which the second information writing impurity is introduced,
A margin for mask alignment is required in the manufacturing process between the first layer gate electrode and the first layer gate electrode. This mask alignment margin increases the gate length of the first layer gate electrode and increases the memory cell area, resulting in a problem of lowering the degree of integration of the vertical mask ROM.

In addition, the present inventor further studied the high integration of the vertical mask ROM described above and found that the following problems also occur.

Each 273rd gate? [The poles have a separation dimension on the first layer gate electrode.] Therefore, in consideration of the distance dimension, it is necessary to increase the gate length of the first layer gate electrode by the distance dimension in design.

An object of the present invention is to provide a technique that can improve the degree of integration of a semiconductor memory device having a vertical mask ROM.

Another object of the present invention is to provide a technique capable of achieving the first object by writing information into a memory cell in a self-aligned manner with respect to the gate electrode.

Another object of the present invention is the first layer of goo! An object of the present invention is to provide a technique that allows writing of information into a memory cell in a self-aligned manner with respect to a first layer gate electrode.

Another object of the present invention is to provide a technique capable of achieving the first object by reducing the gate length of a gate electrode of a memory cell.

Another object of the present invention is to provide a technique capable of reducing the gate length of the first layer gate electrode.

Another object of the present invention is to provide a technique capable of increasing the operating speed of a semiconductor memory device having a vertical mask ROM.

Another object of the present invention is to provide a technique capable of reducing the time required to complete the manufacturing process (hereinafter referred to as shortening the process completion time) in a semiconductor memory device having a vertical mask ROM. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

After forming the second layer gate electrode of a semiconductor memory device having a vertical mask ROM, impurities are introduced into the main surface of the substrate under the first layer gate electrode through the first layer gate electrode, and information Write.

Further, each of the second layer gate electrode and the third layer gate electrode is formed between the first layer gate electrodes or alternately.

[Effect]

According to the above-described means, it is possible to write information (threshold voltage control) in a memory cell configured with the first layer gate electrode in a self-aligned manner with respect to the first layer gate electrode. Therefore, the area of this memory cell can be reduced. In other words, the degree of integration of the vertical mask ROM can be improved.

In addition, since the second layer gate electrode and the third layer gate electrode can be overlapped and the distance between them on the first layer gate electrode can be eliminated, the gate length dimension of the first layer gate electrode can be reduced. Therefore, the area of the memory cell formed by the first layer gate electrode can be reduced. In other words, the degree of integration of the vertical mask ROM can be improved.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I]

FIG. 1 (equivalent circuit diagram) shows a vertical mask ROM which is Embodiment 2 of the present invention.

As shown in FIG. 1, the memory cell array of the vertical mask ROM includes MIS capacitors or MISFETs (hereinafter simply MI
Memory cell Q consisting of SFET).

~Q, are arranged. Memory cells Q1-Q.

are connected in series. 8 pieces (or 16 pieces)

The 32 memory cells Q, ~Q, constitute a unit memory cell row consisting of 8 bits (or 16 bits, 32 bits, etc.).

The memory cell Q is a depletion type (first threshold voltage) that provides "0" information or an enhancement type (second threshold voltage) that provides "'1" information.
It is composed of FET. Memories = Q, -Q, game)? A word line WL extending in two columns is connected to each of the memory cells Q.
It is configured to control conduction and non-conduction of. Each word line WL has one end connected to an X decoder circuit Xdec.
It is connected to the.

The drain/ of the MISFE 'l' constituting the memory cell Q7 of the unit memory cell row, specifically the memory cell Q, is connected to the data 1aDL extending in the row direction and its gate electrode K.
71j is connected to the voltage Vcc of section ' through a precharge MISFE'll'Qp to which a charge signal φp'c is supplied. The power supply voltage Vcc is, for example, a circuit operating voltage of 5 [V]. The data line DL has one end that constitutes a column switch.
Connected to common data line CD through Qs.

The gate electrode of MISFETQs is connected to the Y decoder circuit Ydec. The source of M I 8 F E T constituting the memory cell Qa of the unit memory cell row, specifically the memory cell Q, is connected to the reference voltage Vs.
The reference voltage Vss is, for example, the circuit ground potential 0[:V'!].As will be described later, each of the power supply voltage Vcc and the reference voltage Vss is It is provided in common to each unit memory cell row; it constitutes a power supply voltage wiring and a reference voltage wiring, respectively.

The unit memory cell row has the MI8FET for precharging.
It is composed of a pair of symmetrical shapes in the row direction with Qpc as the center. A plurality of the pair of unit memory cell rows are arranged in a repeating pattern in the row direction and the column direction, forming a memory cell array.

Memory cells configured with enhancement-type MISFETs, such as memory cells Q1 to Q4, are depression-type MISFETs into which impurities are introduced and whose threshold voltages are set to those of the enhancement-type MISFET. As impurities, p-type impurities such as boron (B) and boron fluoride (BFt) are used.

Next, the specific configuration of Example (2) will be explained.

Example of the present invention! The memory cell array of the vertical mask ROM is shown in FIG. 2 (plan view of main parts), and
A cross section taken along the line is shown in FIG.

In FIG. 2, in order to make the configuration of this embodiment easier to understand, insulating films other than the field insulating film provided between each conductive layer are not shown, and data lines and second A part of the gate electrode of the second layer is omitted.

In FIGS. 2 and 3, 1 is a p-type semiconductor substrate (or well region) made of single crystal silicon. A field 1 insulating film 2 and a p-type channel stopper region 3 are provided on the main surface of the semiconductor substrate 1, respectively. Field insulating film 2 and channel stopper region 3 are configured to electrically isolate semiconductor elements. The field insulating films i & 0 are configured to define the shape of the unit memory cell row (specifically, the gate width or channel width dimension of the MISFET in the unit memory cell row).

Memory cells Q and Q8 of the unit memory cell row are formed on the main surface of the semiconductor substrate 1, respectively.

Memory cell Q+ l Qs + Qs + Qy
is composed of a semiconductor substrate 1, a gate insulating film 4, and a first layer gate electrode 5. The memory cells Q, , Q, , Q, , Qa are each composed of a semiconductor substrate 1 , a gate insulating film 8 , and a second Ri-th gate electrode 9 .

Each of the gate insulating films 4.8 is formed of, for example, a silicon oxide film.

The first gate electrode 5 is made of a first conductive layer (gate material) in the manufacturing process, and is made of, for example, a polycrystalline silicon film. The second layer gate electrode 9 is made of the 21st conductive layer (gate material) in the manufacturing process, and is made of, for example, a polycrystalline silicon film. The first layer gate electrode 5 of each memory cell Q, ,Q, ,Q, ,Q has a gate length (channel length)
are arranged at predetermined intervals in the direction. The second layer gate electrodes 9 of each of the memory cells Q2゜Q, , Q, , Q, are stacked on top of the first layer gate electrodes 5 at their respective ends between the first layer gate electrodes 5. It is arranged like this.

A word line (WL) 5A is formed integrally with the first layer gate electrode 5 of each of the memory cells Q, , Q, , Q, , Q. Memory cell Q
, ,Q, ,Q, ,Q, each of the two threatening gate electrodes 9 has a word line (WL) 9A formed integrally therewith.

Further, each of the gate electrodes 5.9 is made of a high melting point metal (Mo,
Ti, Ta, W) film or high melting point metal silicide (F
vfoSi, , TiSi2. Taxi! , WSi2) film. Furthermore, each of the gate electrodes 5.9 may be formed of a composite film in which a high melting point metal film or a high melting point metal silicide film is superimposed on a polycrystalline silicon film.

Each of the memory cells Q, ~Q, is configured to be a depression type MISFET and have a low threshold voltage when no information is written therein.

That is, although not shown, the main surface of the memory cell formation region of the p-type semiconductor substrate 1 is made n-type by introducing an n-type impurity (for example, phosphorus).

A p-type semiconductor region 7A is provided in the threshold voltage control region (channel region) of the memory cells Q1 and Q in which information is written.
is provided. Similarly, p-type semiconductor regions 6 are provided in the threshold voltage control regions of memory cells Q and Q4 in which information is written. Each of the semiconductor regions 7A and 6 is configured to change a plurality of MIspErs having a depletion Y type, that is, a low threshold voltage, into an enhancement type, that is, a MISFET having a high threshold voltage.

As will be described in detail later, the semiconductor region 7A is formed in a self-aligned manner with respect to the first layer gate electrode 5, and the semiconductor region 6 is
It is formed in a self-aligned manner with respect to the first layer gate electrode 5. In a deep region within the semiconductor substrate 1 below the semiconductor region 6, p
A type semiconductor region 7B is formed. The deep region is a region other than the threshold voltage control region of each of memory cells Q1 and Q4. The semiconductor region 7B is formed in the same process as the semiconductor region 7A, but the memory cells Q1 and Q
4 is formed in a region where the respective threshold voltages are not changed.

At one end side (memory cell Q side) of the unit memory cell row configured in this way, there is a MI8FE'l' for precharging.
Qpc is connected. M I S F ETQpc
is formed on the main surface of the semiconductor substrate 1, and includes a gate insulating film 4,
It is composed of a gate electrode 5 and a pair of n+ type semiconductor regions 10 which are source regions or drain regions. M.I.S.
The connection between FETQpc and unit memory cell row is MISF
A semiconductor region 10 which is a source region of ETQpc is a memory cell Q.

This is done by sharing the drain region of the two.

Semiconductor region 1 which is the drain region of MISFETQpc
0 is connected to a wiring (power supply voltage wiring) 13 to which a power supply voltage Vcc is applied. The wiring 13 is electrically connected to the semiconductor region 10 through a connection hole 12 formed on the glabellar insulating film ll made of, for example, a 7-osilicate glass (PSG) film, and extends. Wiring 13
is formed as the first layer in the manufacturing process, for example, an aluminum film or an aluminum film containing predetermined additives (Cu, Si).

Drain region of memory cell Q and MI 8 FBTQ
The semiconductor region 10, which is the source region of the PC, contains data!
(DL) 16 is connected. The data line 16 extends on the interlayer insulating film 14 made of, for example, a PSG film and is electrically connected to the semiconductor region 10 through a connection hole 15 formed therein.

The data line 16 is formed of the same aluminum film as the second layer wiring in the manufacturing process, for example, the arrangement a13.

At the other end of the unit memory cell row (memory cell Qs (Qll), there is a wiring (reference voltage wiring) to which the reference voltage Vss is applied via an n+ type semiconductor region 10 serving as a source region of the memory cell Q. m) 13 is connected to 0.Next, regarding the manufacturing method and information writing method of the vertical mask ROM configured in this way, FIGS. 4 to 7 (the memory cell array shown for each manufacturing process) This will be briefly explained using a cross-sectional view of main parts.

First, as shown in FIG. 4, a field insulation g2, a p-type channel stopper region 3
form each.

Next, on the main surface of the semiconductor substrate 1 in the semiconductor element formation region,
A gate insulating film 4 is formed. The gate insulating film 4 is formed using, for example, a silicon oxide film formed by oxidizing the surface of the semiconductor substrate 10, and has a thickness of about 100 to 300 [Xa]. Although not shown, after this, the main surface of the semiconductor substrate 1 is exposed through the gate insulating film 4 to the region where the memory cell is formed, that is, the MI of the memory cell, and the threshold voltage control region (channel region) of the 9FET. Introducing impurities to adjust the threshold voltage. The impurity that adjusts the threshold voltage depletes the memory cell Q.
In other words, it is introduced to provide an M I S FET with a low threshold voltage. The impurity is an n-type impurity (A s
, P) by ion implantation.

Next, for example, Chemical Vapor Dep.
A polycrystalline silicon film is formed on the main surface of the semiconductor substrate by a chemical vapor deposition (CVD) method, and then the polycrystalline silicon film is buttered to form a first layer gate electrode 5 on a predetermined upper part of the gate insulating film 4. Form. For the first layer gate electrode 5, for example, a polycrystalline silicon film doped with impurities (As, P) may be used for the purpose of reducing the resistance value of the gate electrode 5. The polycrystalline silicon film has a thickness of 300
It is formed with a film thickness of about 0 to 10,000 (A). This first
In the step of forming the layered gate electrode 5, memory cells Q, , Q, , Q, and Q made of MISF'ET are formed.

Next, as shown in FIG. 5, the memory cell Q and Q4 formation regions (the region where the second layer gate electrode 9 between the first layer gate electrodes 5 is to be formed) are opened for impurity introduction. A mask 17 is formed. The mask 17 is formed so that its opening end is located above the first layer gate electrode 5, taking into account mask misalignment during the manufacturing process. The mask 17 is formed of, for example, a photoresist film.

Next, the semiconductor substrate 1 in the memory cell Q2 and Q4 forming region is
An impurity 6a for writing the first information is introduced onto the surface of the substrate 0, and the first information is written.

The information writing impurity 6a is introduced using the mask 17 and the first layer gate electrode 5 exposed from the mask as masks. The impurity 6a is introduced into the threshold voltage control region of each of the memory cells Q2 and Q4, and converts these 0Ml5FETs into depletion type MISFETs with low threshold voltages.
ET is set to an enhancement type MISFBT having a high threshold voltage. Impurity 6a is
Poron fluoride (BFz) with an impurity concentration of about 1X10"-3X10'8 (atoms/crA) is used. The impurity 6a is a low energy material, for example, about 60 (KeV), which does not pass through the first WJ gate electrode 5. The impurity 6a introduced under these conditions has an impurity concentration of O to 30 o (X
) has a peak at a depth of approximately

In this way, after forming the first layer gate electrode 5 on the semiconductor substrate 1, the main portion of the semiconductor substrate 1 between the first layer gate electrodes 5 (the area where the second layer gate electrode 9 is to be formed) is Since the impurity 6a is introduced into the surface part and the information is written for the first time, the impurity 6a for information writing is introduced using the first layer gate electrode 5 as a mask. The information writing impurity 6a can be introduced in a self-aligned manner. That is, memory cells Q2, Q.

The information is written to the 17th ifl gate electrode 5.
Since it can be performed in a self-aligned manner with respect to the memory cell Q, the mask alignment margin in the manufacturing process can be reduced and the
The area of ~Q can be reduced.

Next, the mask 17 is removed, and as shown in FIG.
An impurity introduction mask 18 having openings is formed. The mask 18 is formed so that the opening end thereof is located on the second m-th gate electrode 9 formation region into which the impurity 6a is introduced, taking into account mask misalignment during the manufacturing process.

The mask 18 is formed of, for example, a photoresist film.

Next, impurity 7a is added to the surface of the semiconductor substrate l in the memory cell Q1 and Q3 regions (below the first eyelet gate electrode 5) in order to write second information through the first layer gate electrode 5. Write the information for the second time. The impurity 7a is introduced using the mask 18 and the first layer gate electrode 5 exposed therefrom as masks. Impurity 7a is in memory cell Q
1.Q.

are introduced into the threshold voltage control region of each of these M
The ISFET was changed from a depression type MI8F'ET with a low threshold voltage to an engineering type MI8F'ET with a high threshold voltage.

Impurity 7a is I x 10” to 3 x 10” l
Boron (B) is used at an impurity concentration of about 1000 atoms/cA).

The impurity 7a is introduced by high-energy ion implantation, for example, about 300 (KeV), which passes through the first layer gate electrode 5. Note that the mask 18 is formed to be sufficiently thick so that impurities do not pass through this ion implantation. Memory cell Q exposed in the opening of mask 18! , in the Q4 formation region, the first N! 1st gate 1
! Since it does not pass through the pole 5, the impurity 7a is introduced into a deep region within the semiconductor substrate 1 other than the threshold voltage control region.

That is, in the memory cells Q2 and Q4 forming regions, the information writing impurity 7a is introduced into a region that does not affect the threshold voltage. The impurity concentration of the impurity 7a introduced under these conditions has a peak at a depth of about θ˜300 [A] from the surface of the semiconductor substrate 1 in the memory cell Q, , Q, region. Further, in the memory cells Q, , Q, and the formation region, the impurity concentration of the impurity 7a is 3000 to 10000. It has a peak at a depth of about [A].

In this way, after forming the first layer gate electrode 5 on the semiconductor substrate l, the semiconductor substrate 1 under the first layer gate electrode 5 is
By introducing the second information writing impurity 7a into the main surface portion through the first layer gate electrode 5 and performing the second information writing, a memory cell configured with the first layer gate electrode 5 is formed. Information writing (threshold voltage control) of QlsQ3 can be performed in a self-aligned manner with respect to the first layer gate im pole 5. That is, there is no need for a mask alignment margin in the manufacturing process between the first layer gate electrode 5 and the region into which the impurity 7a is introduced. Therefore, the gate length of each of the first layer gate electrode 5 and the second layer gate electrode 9 is set to be d smaller than the memory cell Q.

~ Q6 Since the area can be reduced, vertical mask R
The degree of integration of OM can be significantly improved.

In addition, since the gate length of each of memory cells Q1 to Q8 can be made smaller and the series resistance value of a unit memory cell row can be reduced, the drawing speed of the precharge potential in the information read operation can be increased, and the vertical The operating speed of the mask ROM can be increased.

Further, the second information writing is performed by introducing the information writing impurity 7a through the first layer gate electrode 5 after forming the first layer gate electrode 5. When writing the second information before forming the electrode 5, it is possible to completely shorten the space.

After the second information writing shown in FIG. 6, the mask 18 is removed, and the information writing impurity 7 is removed.
The gate insulating film 4 between the first Aj-th gate electrodes 5 contaminated by the implantation of a is removed by light etching. After that, as shown in FIG. 7, a new memory cell Q2 is added.
, Q, , Q, and Q8 forming region (between first layer gate electrodes 5), a gate insulating film 8 is formed. The gate insulating film 8 is a silicon oxide film formed by oxidizing the surface of the semiconductor substrate 10, and then a second Δ-th gate electrode 9 is formed on the gate, l;
form. The second layer gate 1c pole 9 is, for example, the first
Similarly to the layered gate electrode 5, a polycrystalline silicon film is formed on the main surface of the semiconductor substrate 1 by the CVD method, and then patterned by etching. The second layer gate electrodes 9 patterned by the etching are formed so as to be spaced apart from each other on the first layer gate electrode.

Through this step of forming second layer gate electrode 9, memory cells Q, , Q, , Q, and Q are formed.

Next, precharge M I S F E T Q p
N-type semiconductor regions 10 are formed on both sides of the gate 'Ilf electrode 5 and on one side of the memory cell Q. The semiconductor region 10 can be formed by introducing an n-type impurity (for example, As) by ion implantation using the gate electrodes 5 and 9 as a mask, and then performing an annealing (heat treatment) ″f′. information writing impurity 6a,
7a are formed in each of the p-type semiconductor regions 6.7A and 7B by an annealing process or the like for forming the semiconductor region 10.

Next, by sequentially forming the interlayer insulating film 11, connection hole 12, wiring 13, interlayer insulating film 14, connection hole 15, and data line 16, the vertical type shown in FIGS. 2 and 3 is formed. Mask 1% OM is completed.

Note that in the present invention, the first information writing and the second information writing may be exchanged.

That is, the present invention introduces the impurity 7a through the first layer gate electrode 5 after the step of forming the first layer gate electrode 5, and then introduces the impurity 6a between the first layer gate electrodes 5.
You may introduce a.

In addition, the invention is to set the memory cells Q and -Q to enhancement type M I 8 F E 'I' in advance, and by introducing impurities into the predetermined memory cell Q.
may be set to a low threshold f+fE voltage such that it becomes a depletion type MI8FET. In this case, an n-type impurity such as As or P is used as the impurity.

[Example ■]

In this embodiment (2), the first JV! i
This is another embodiment of the present invention in which the depthwise position of the information writing impurity introduced into the first gate Ms, the very bottom, and below the second layer gate electrode can be controlled.

A vertical mask ROM according to the embodiment (2) of the present invention is shown in FIG. 8 (a sectional view of the main part in a predetermined manufacturing process).

In Example H, prior to writing information under the first layer gate electrode 5, a mask 19 is formed above the first layer gate electrode 5, and then the impurity 7a is introduced by ion implantation. For example, the mask 19 is formed (cut in an overlapping manner) at the same time as the first layer gate electrode 5 is processed (etched). That is, on the polycrystalline silicon layer for forming the gate electrode 5 deposited over the entire surface of the substrate,
Furthermore, a silicon oxide film or a silicon nitride film is formed by, for example, CVD, and then these insulating films are etched by anisotropic etching such as RIE (reactive ion etching) using a photoresist film (not shown). Then, the polycrystalline silicon is sequentially etched to form a first layer gate electrode M pole 5 and a mask 19. Also, mask 1
Reference numeral 9 may be formed of an etching mask used for processing the first layer gate electrode 5, that is, a photoresist film.

In this case, both of the masks 18 and 19 should not be of positive type (or one or both should be of negative type).

In this way, the mask 19 is formed on the top of the first layer cathode electrode 5 in a self-aligned manner, and the impurity is passed through both layers. ! 1
7a is introduced to write information under the first Hi MIG-% pole 5. As a result, the implantation energy of the impurity 7a can be increased using the mask 19, so that under the first layer gate electrode 5! A sufficient difference in the positions of the impurities 7a introduced under the second layer gate electrode 9 can be ensured (the difference in positions can be increased). That is, when energy is selected to introduce the impurity 7a into the substrate surface of the memory cells Q, Qt, the impurity 7a introduced under the region where the memory cells Qt, Q= are to be formed is ,
It can be formed at a deep position so as not to affect the threshold voltage of Q. As a result, the reliability of information writing in the vertical mask (OM) can be improved.

In this Example (2), the ion implantation of the impurity 6a and other steps are performed on the same machine as in Example I.

[Example ■]

Embodiment 2 is another embodiment of the present invention in which the separation dimension between the second layer gate electrodes of a unit memory cell row is reduced and the degree of integration of the vertical mask ROM is further improved.

A memory cell array of a vertical mask ROM according to Embodiment 2 of the present invention is shown in FIG. 9 (cross-sectional view of main parts), FIG. 10 (cross-sectional view of main parts), and FIG. 11 (cross-sectional view of main parts).

In this embodiment (2), instead of the second layer gate electrode 9 in the embodiment (2), a second layer gate 1JL pole 9A and a first layer gate electrode 5) 9B are alternately formed. The portions under the first layer gate electrodes 5 are arranged every other time between the first layer gate electrodes 5. The third layer gate electrode 9B is the second layer gate electrode 9
After forming the second layer gate electrodes 9, the second layer gate electrodes 9 are placed between the first layer gate electrodes 5. In other words, each of the second layer gate electrode 9A and the third J'eJ-th gate electrode 9B is as follows.
They are alternately formed between the first layer gate electrodes 5 in the gate length direction.

That is, the end to the second layer gate electrode 9 and the end of the third layer gate electrode 9B are formed so as to overlap on the first layer gate electrode.

The vertical mask i-LOM configured in this manner overlaps the second layer gate electrode 9A and the third Ir first gate electrode 9B, and creates a gap between them (9A and 9B) on the first layer gate electrode 5. Dimensions can be eliminated. That is, the distance between each gate electrode 90 in Example IK (usually,
minimum processing dimensions) are not required. Therefore, in consideration of the above-mentioned separation dimension, the gate length dimension of the first layer gate electrode 5 is designed to be long (there is no need to estimate it, so the first Jv1
The gate length dimension of the first gate electrode 5 is reduced, and the memory cells Q, , Q, , Q are configured with the first layer gate electrode 5.

And the area of Q7 can be reduced. In other words, the degree of integration of the vertical mask ROM can be further improved.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the vertical mask (LOM) of the present invention is PLA.
(Programmable Logic Array
) and other logic circuits. For example, as shown in FIG.
With the same configuration as Ydec, a part of the Y decoder circuit
l can be constructed. In FIG. 12, Yde
cl is a unit memory cell row and MISFE for precharging
The unit selection circuit of the OY decoder Ydecl, which is connected between the OY decoder Ydecl and the unit memory cell row TQpc and selectively connects the unit memory cell row to the data line DL, is composed of M ISF E T Q d , ~
Consists of Q d n. MISFET Qd.

˜Qdn is of the depth type or enhancement type according to the present invention. One unit selection circuit corresponds to one memory cell row. The Y decoder Ydecl has
A predetermined portion of complementary address signals generated in an address buffer circuit (not shown) is supplied;
MISFET Qd.

~Q d n etc. are supplied to each gate electrode. The vertical mask ROM shown in FIG. 10 has M
It is constructed by symmetrically arranging ISFETQpc, Y decoder Ydecl, and memory cell array, and repeating this process. Of the plurality of unit memory cell rows corresponding to the same data line, one selected by the Y decoder Ydecl is connected to the data line. In this case, the Y decoder Ydecl is not a memory circuit, but a 1
It can be seen as a logic circuit that selects one memory cell row in response to an external signal.

In particular, in a vertical mask ROM, the degree of integration can be further improved by making part of the Y decoder have the same structure as the memory cell array, as shown in FIG.

Moreover, it is possible to implement the above-mentioned Examples 1 to 2 in combination.

M configuring the peripheral circuit of the memory cell 1. S F E
TQpc etc. are known LDD (Lightly
DopedDrain) structure, D D D (Dou
It may also be a cross-piece structure such as a ble Diffused Drain structure.

The memory cell array is a p-type semiconductor substrate formed in an n-type semiconductor substrate.
- may be formed within the type well region.

The present invention is also effective for semiconductor integrated circuit devices, such as a one-chip microcombinator, in which a vertical mask l-LOM is formed on the same semiconductor substrate together with other logic circuits.

The gate electrode (word line) may be formed by repeating four or more conductor layers.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

After forming the first layer gate electrode of the vertical mask ROM, this layer is formed on the main surface of the substrate under the first layer gate electrode.
By introducing an impurity for information writing through the gate electrode of the first layer and writing information, writing of information in the memory cell constituted by the gate electrode of the first layer can be performed for the 17th mth layer gate electrode. Since this can be done in a self-aligned manner, the memory cell area can be reduced and the degree of integration of the vertical mask ROM can be improved.

In addition, each of the 21st layer gate electrode and the 3rd layer gate electrode is
By forming alternately between the first and second gate electrodes, the second and third gate electrodes and the third and fourth gate electrodes are superimposed,
Since it is possible to reduce the distance between the two on the first layer gate electrode, the gate length of the first layer gate electrode can be reduced, and the area of the memory cell configured with the first layer gate electrode can be reduced. However, the degree of integration of the linear mask ROM can be further improved.

[Brief explanation of the drawing]

FIG. 1 shows a vertical mask)tOM which is an embodiment of the present invention.
2 is a plan view of essential parts showing the memory cell array of the vertical mask ROM, FIG. 3 is a sectional view taken along nt-nta in FIG.
7 to 7 are cross-sectional views of main parts of each manufacturing process of the memory cell array shown in FIG. 3, and FIG. FIG. 9 is a cross-sectional view of a main part showing a memory cell array of a vertical mask ROM used for actual measurement of the present invention, and FIG. Vertical mask) LOM, a cross-sectional view of the main part showing the memory cell array in a predetermined manufacturing process, Figure @11 is a Pino r blood diagram cut at the IV-IV gland in Figure 9, and Figure 12 is a cross-sectional view of the main part of the memory cell array in a predetermined manufacturing process. FIG. 3 is a circuit diagram showing another example of application of . In the figure, 1: semiconductor substrate, 4, 8: gate insulating film, 5.9, 9A, 9B: gate electrode, 5A, 9A. WL... Word line, 6, 7A, 7B, 10... Semiconductor region, 5a, 7a... Impurity for information writing, 13...
・Wiring, 16, DL...Data Fuji, 17, 18.
19...Mask, Q1-Q,...Memory cell, Qp
c...MISFET. Agent: Patent Attorney Katsuo Ogawa 7,1--,,
/

Claims (1)

[Claims] 1. Manufacture of a semiconductor integrated circuit device having a vertical mask ROM in which a second layer gate electrode is formed between a plurality of first layer gate electrodes arranged at predetermined intervals in the gate length direction. The method includes the steps of forming a first layer gate electrode on a substrate, and using the first layer gate electrode as a mask, impurities for information writing are added to the main surface of the substrate between the first layer gate electrodes. and a step of forming a second layer gate electrode on the main surface of the substrate on which the first information is written, After the step of forming the electrode or after the step of writing the first information, an impurity for information writing is introduced into the main surface of the substrate under the first layer gate electrode through the first layer gate electrode. . A method of manufacturing a semiconductor memory device, comprising the steps of writing second information. 2. Manufacturing the semiconductor memory device according to claim 1, wherein each of the first layer gate electrode and the second layer gate electrode constitutes a memory cell consisting of an MIS diode. Method. 3. In the step of writing the first information, impurities for information writing are introduced by ion implantation at a low energy level that does not pass through the first layer gate electrode, and the step of writing the second information is as follows: A method for manufacturing a semiconductor memory device according to claim 1 or 2, characterized in that the information writing impurity is introduced by high-energy ion implantation that passes through the first layer gate electrode. . 4. In the step of writing the second information, impurities for information writing are introduced into the threshold voltage control region under the first layer gate electrode, and the threshold voltage control region is introduced under the second layer gate electrode. 4. A method of manufacturing a semiconductor memory device according to claim 1, wherein an impurity for information writing is introduced into a region other than the voltage control region. 5. Claims characterized in that a mask such as an insulating film or a photoresist film is formed on the first layer gate electrode in a self-aligned manner with respect to the first layer gate electrode. Each of the methods for manufacturing a semiconductor memory device according to items 1 to 4. 6. The mask is configured to control the position of information writing impurities introduced under the first layer gate electrode and under the second layer gate electrode, respectively, in the step of writing the second information. Claim 5 characterized in that:
A method for manufacturing a semiconductor memory device according to paragraph 1. 7. The step of writing the first and second information is a step of setting the threshold voltage under the second layer and the first layer gate electrode from a depletion type to an enhancement type or vice versa. Claim 1 characterized in that
A method of manufacturing a semiconductor integrated circuit device according to each of items 6 to 6. 8. A semiconductor memory device includes: a semiconductor substrate having a main surface; an insulating film formed on the main surface of the semiconductor substrate; a first conductive layer formed on the insulating film; and a first conductive layer formed on the insulating film. a second conductive layer formed on the insulating film and overlapping at least a portion of the first conductive layer; and a third conductive layer formed on the insulating film and overlapping at least a portion of each of the first and second conductive layers. The present invention is further characterized in that a plurality of MISFETs connected in series are formed by using each of the first, second, and third conductive layers as a gate electrode of a MISFET. 9. In the semiconductor memory device according to claim 8, some of the plurality of MISFETs connected in series are depletion type, and the remaining plurality of MISFETs are of the depletion type.
is an enhancement type. 10. The semiconductor memory device according to claim 8, wherein the first, second and third conductive layers are made of polycrystalline silicon. 11. The semiconductor memory device according to claim 8, wherein the plurality of MISFETs include memory cells of a vertical ROM. 12. A plurality of first gates arranged at predetermined intervals in the gate length direction
A method for manufacturing a semiconductor memory device having a vertical mask ROM in which a gate electrode of an upper layer is formed between layer gate electrodes, the method comprising: forming a first layer gate electrode on a substrate; a step of introducing an impurity for information writing into a main surface portion of the substrate between the first layer gate electrodes using the second layer gate electrode as a mask and writing first information; and a step of writing first information; The second layer and the third layer are formed on the main surface of the substrate in the gate length direction.
after the step of forming the first layer gate electrode or after the step of writing the first information, A method of manufacturing a semiconductor memory device, comprising the step of introducing impurities for information writing into the principal surface of the substrate through the first layer gate electrode and writing second information. 13. A semiconductor memory device includes: a semiconductor substrate having a main surface; an insulating film formed on the main surface of the semiconductor substrate; a plurality of first conductive layers arranged in a row on the insulating film; a first second conductive layer that is formed on an insulating film and that at least partially overlaps each of two adjacent first conductive layers selected from the plurality of first conductive layers; The second conductive layer is provided extending between the two adjacent first conductive layers, is formed on the insulating film, and is formed close to one of the two adjacent first conductive layers. a second second conductive layer that at least partially overlaps another first conductive layer; the second second conductive layer and the first second conductive layer are formed apart from each other; a third conductive layer formed on the insulating film and at least partially overlapping the first and second second conductive layers, the third conductive layer being the first and second second conductive layers; M is formed extending between two conductive layers, and further includes M
By using it as a gate electrode of an ISFET, a plurality of MISFETs connected in series are formed, and some of the plurality of MISFETs connected in series are made into a depletion type, and the remaining plurality of MISFETs are made into an enhancement type. It is characterized by 14. The semiconductor memory device according to claim 13, wherein the plurality of MISFETs connected in series include memory cells of a vertical read-only memory. 15. In the semiconductor memory device according to claim 13, the plurality of MISFETs connected in series have a vertical mask R.
It is characterized by including OM memory cells. 16. The semiconductor memory device according to claim 13, wherein each of the first, second and third conductive layers is made of a polycrystalline silicon layer. 17. The semiconductor memory device according to claim 13, wherein the semiconductor memory device is formed by a three-layer polysilicon process.