JPH01117366A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a quality MESFET provided with a source, a gate, and a drain with the gaps between them constant and smaller and provided with a gate electrode enhanced in thickness by a method wherein a trench is provided in the surface of a semiconductor layer and, in the trench, a Schottky junction is formed between a gate electrode buried in the trench and the semiconductor layer for the construction of a MESFET. CONSTITUTION:On the semi-insulating GaAs substrate 11, an N-type layer 12 is epitaxially grown. Onto the entire surface of such a wafer, an AuGe layer and then an ohmic metal layer 13 are attached. Heat treatment is accomplished, which is followed by patterning whereby a 2.5mum gap is provided between a source and a drain. The ohmic metal layer 13 and the N-type layer 12 are then subjected to ion beam etching. A plasma SiO2 film 14 is provided and subjected to etching which is accomplished vertical to the substrate surface. Next, three layers of Ti, Pt, and Au are laid on the entire surface, in that order. Ion beam etching is accomplished at 30 deg. to the direction vertical to the substrate surface, after which Au and Pt are retained only at a gate section 15. Etching follows, after which Ti is retained only under the gate section 15 for the completion of a three-layer Schottky gate electrode.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
It is used for MESFETs and integrated circuits using them.

(Conventional technology) A conventional example of this type of semiconductor device is shown in FIG.

In the figure, 1 is a GaAs substrate (semi-insulating substrate), 2 is an N-type layer,
31 is an ohmic metal that becomes the source electrode, 3! 4 is an ohmic metal serving as a drain electrode, and 4 is a Schottky metal serving as a gate electrode.

The conventional method of fabricating this semiconductor device is to grow an N-type layer 2t on a semi-insulating substrate 1, perform mesa etching to leave only the desired portion, and then remove the source and drain electrodes (Jt m3).
s)'k, formed by AuGe/Pt lift-off method, heat treated, 74 turn of gate, recess etching, and then gate electrode 4'lt
It is formed by a lift-off method, and a metal is connected to the electrode 31e3 to form a GaAs MESFIT.

This MESFET has an amplification effect by controlling the depletion layer formed under the gate electrode 4 through a Schottky junction between the gate electrode 4 and the N-type layer 2, and extracting the current between the source and drain according to the gate input. etc.

(Problems to be Solved by the Invention) In the prior art described above, in order to improve the characteristics, the width of the gate electrode 4 is made as small as possible, and the width of the thin part of the N layer 2 on the source side and the drain side is made small. Although attempts were made to minimize the resistance, the yield was poor because the gate electrode 4 was formed by mask alignment. Although the above conditions can be improved by using an electron beam exposure device, this device has the drawbacks of being expensive, having poor throughput, and limiting the types of resists that can be used. Furthermore, since the lift-off method was used, there were severe restrictions on the conditions for metal vapor deposition and resisting. In addition, the lift-off method does not allow the metal to be made thicker, which has the disadvantage of increasing gate resistance.

The present invention was made in view of the above circumstances, and while the conventional technology relied on mechanical precision for gate positioning, it is possible to perform self-alignment and form 4 fine turns of the gate with good characteristics. By doing so, it attempts to eliminate the problems of the past.

[Structure of the invention] (Means and effects for solving the problems) The present invention provides a semiconductor layer of a certain conductivity type on a compound semiconductor substrate, a recessed portion on the surface of the core layer, and a layer containing the recessed portion. An insulating film is provided on the semiconductor layer, the insulating film is left only on the side walls of the recess by anisotropic dry etching, and an r-) electrode is provided so as to be buried in the recess covered with the insulating film. MESF is performed by forming a Schottky junction between the electrode and the semiconductor layer.
ET! A method of manufacturing a semiconductor device is characterized by forming a semiconductor device.

That is, the present invention uses anisotropic dry etching to leave an insulating film only on the side walls of the recess (self-alignment), and covers the inside of the recess with this insulating film. -) By providing electrodes, the spacing between the source, gate, and drain can be made constant and small, and the thickness of the gate electrode can be increased, resulting in an ME with good characteristics.
It is a friend that allows SFET to be obtained.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
This figure is the ninth sectional view fully explaining the same embodiment. As shown in the figure, N-type layers 12f0.
A 5 μm epitaxially grown wafer is used. The entire surface of this wafer is covered with AuG (5% G in Au) t-thickness zoool, and on top of that is Ni (Pt is also acceptable) t-30.
Ohmic metal 13 (131 will be the source electrode, 13 will be the drain electrode) provided with 0X T-deposited and heated at 430°C
, heat-treated in hydrogen for 5 minutes, cut and turned 2.5 μm between the source and drain, and etched the ohmic metal 13 and N-type layer 12 by ion beam etching.
Etch to a depth of about 0.3 μm. After that, Grazma Si
O□HI1.14 is deposited to a thickness of 1.1 μm, and etched perpendicularly to the substrate surface by fully reactive ion etching (anisotropic dry etching). As a result, as shown in FIG. 1, the plasma 810□ film 14 remains only on the sidewalls of the recesses in the layer on the substrate 11. Next, to obtain the gate part, use T12000X using the snow and ivy method.

Three metal layers of PT SO O^ and Au50001 are deposited on the entire surface in this order, and etched by ion beam etching at an angle of 30' with respect to the direction perpendicular to the substrate.
Only the Au and Pt of the gate portion 15 remain. At this time r-
Since the etching rate of Tl is low in areas other than the top portion 15, T1 remains on the entire surface. Therefore, by etching with this Tlt-ammonium fluoride and leaving Tlt- only under the gate portion 15, a three-layer sheet key gate electrode 15 is formed. Thereafter, unnecessary parts of the N layer 12 on the GaAs substrate 11 are mesa-etched, leaving only the parts necessary for the operation of the eight layers 12, and the electrodes J 31 , 13 . , GaAs-MESF
ET ¥i' is what you get.

By the method described above, the distances A, B, and C between the source, gate, and drain can be kept constant and shortened by self-alignment using the plasma 5102 film 14 shown in FIG. 1, so that the source resistance and drain resistance can also be reduced. This can improve the characteristics of the MESFET. Furthermore, since the thickness of the gate electrode 15 can be made larger than when using the conventional lift-off method, the gate resistance can be reduced. In addition, since the present invention allows fine processing,
0.4μm without using special lithography for turns
4 turns of thickness of )f-) were formed.

By this method, the source spacing A and the gate spacing B could be made particularly thin, so that the values of the noise figure NF = 1.4 dB and the gain Ga = 9 dB were obtained at 12 GHz by high frequency measurement.

[Effects of the Invention] As explained above, according to the present invention, the following advantages are obtained: the distance between the source, gate, and drain can be made constant and small, the gate electrode thickness can be increased, and an MBSFET with good characteristics can be obtained. It is something.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of an embodiment of the present invention.
It is an explanatory diagram for obtaining ESFET 't'. 11 = GaAm substrate, 12 ・N-type layer, 13-...
Ohmic metal, 131... source electrode, 132...
...Drain electrode, 14...Plasma S10□ film, 1
5...Silicon key metal (gate electrode).

Claims (2)

[Claims] (1) A semiconductor layer of a certain conductivity type is provided on a compound semiconductor substrate, a recess is provided on the surface of the layer, an insulating film is provided on the semiconductor layer including the recess, and the recess is removed by anisotropic dry etching. The insulating film is left only on the side walls of the M, and a gate electrode is provided so as to be buried in the recess covered with the insulating film to form a Schottky junction between the gate electrode and the semiconductor layer.
A method for manufacturing a semiconductor device, comprising forming an ESFET. (2) Schottky metal is deposited on the entire surface of the gate electrode, including the recess, and the Schottky metal is etched by irradiating an ion beam from a direction at an angle with respect to the direction perpendicular to the substrate surface. A method of manufacturing a semiconductor device according to claim 1, which is formed by: