JPH01123329A - Interrupting circuit - Google Patents

Abstract

PURPOSE:To detect the changes of all the terminal states even when two or more input terminal states change at the same time by providing a means with a latch circuit to execute the latch of an input signal and an output from the latch circuit with a clock control, and generate an interrupting signal by the exclusive OR of the latch output. CONSTITUTION:When a clock signal 141 is generated in the timing of ct4, a latch circuit 140 latches the input state of a terminal D, and a latch output 142 changes from a low level to a high level. An exclusive OR signal 301 becomes the low level by the exclusive OR of latch outputs 112, 122, 132, and 142, and an edge detecting circuit 320 detects the fall edge of the exclusive OR signal 301, outputs a setting signal 302, and sets an interrupting flag 330. A central processing unit outputs a strobe signal 341, makes an internal bus 350 output the input state of each terminal through an input buffer 340, and judges a interrupting factor. Thus, all the terminal states can be detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-input interrupt circuit, and in particular, even if the states of two or more of a plurality of interrupt input terminals change simultaneously, the input terminal state remains unchanged. The present invention relates to an interrupt circuit that can detect changes in .

[Conventional technology]

Conventional multi-input interrupt circuits use exclusive OR means to detect a change in the state of at least one input terminal, regardless of the initial state of the input terminal.

FIG. 5 is a block diagram showing a conventional multi-input interrupt circuit.

This circuit has terminals A, B, C, D, and an exclusive OR circuit 31.
0, an edge detection circuit 320, an interrupt flag 330, an input buffer 340, and an internal bus 350.

In FIG. 5, terminals A, B, C, and D are input terminals for interrupt signals.

The exclusive OR circuit 310 has terminals A, B, and C.

This is a four-person exclusive OR circuit which takes the input signal of D as an input, performs an exclusive OR, and outputs an exclusive OR signal 3-01.

The edge detection circuit 320 is a double edge detection circuit that detects both rising and falling edge changes of the exclusive OR signal 301 and outputs a set signal 302.

The interrupt plug 330 is activated by the set signal 302.
A 1-bit interrupt flag set to "1" notifies the central processing unit (not shown) of the occurrence of an interrupt request. Interrupt plug 330 is cleared as soon as the central processing unit starts interrupt processing.

The input buffer 340 has terminals A and B in response to an input strobe signal 341 output from the central processing section.

The states of C and D are output to the internal bus 350.

Next, the conventional operation will be explained.

FIG. 6 is a time chart showing the operation of the conventional example. When terminal A is at high level, terminal B is at low level, terminal C is at high level, and terminal C is at low level, terminal C goes high at timing tl. From level to low level,
Next, a case will be shown in which the terminal B changes from a low level to a high level at timing t2, and further, the terminal A changes from a high level to a low level at a timing t3, and the terminal B changes from a low level to a high level at the same time.

When the terminal C changes from high level to low level at timing t1, the exclusive OR signal 301 becomes high level, and the edge detection circuit 320 outputs the exclusive OR signal 301.
The rising edge of is detected, a set signal 302 is output, and an interrupt flag 330 is set. The central processing unit starts interrupt processing, outputs a strobe signal 341 in the interrupt processing, outputs the input state of each terminal to the internal bus 350 via the input buffer 7340, and determines the cause of the interrupt. The central processing unit can identify the terminal C whose state has changed by reading the input state of each terminal output to the internal bus 350, and executes processing corresponding to the change in the input of the terminal C.

Next, when the terminal B changes from low level to high level at timing t2, the exclusive OR signal 301 becomes low level, the edge detection circuit 320 detects the falling edge of the exclusive OR signal 301, and the set signal 302 is output and the interrupt flag 330 is set. The central processing unit starts interrupt processing, outputs a strobe signal 341 in the interrupt processing, outputs the input state of each terminal to the internal bus 350 via the input buffer 340, and determines the cause of the interrupt. By reading the input status of each terminal output to the internal bus 350, the central processing unit can identify the terminal B whose status has changed, and executes processing corresponding to the input change of the terminal B.

However, if terminal A changes from high level to low level and terminal A changes from low level to pi level at timing t3, the exclusive OR signal 301 remains at low level, so edge detection cannot be performed and the interrupt flag is is not set, the central processing unit does not start interrupt processing.

In other words, when the terminal states of terminals A and D changed simultaneously at timing t3, it was not possible to detect the state change of either terminal.

[Problem that the invention seeks to solve]

Since the conventional multi-input interrupt circuit described above uses exclusive OR circuit means, it has the problem that when two or more input terminals change simultaneously, it is impossible to detect a change in the state of any of the terminals.

[Contents of differences between the invention and the prior art] In contrast to the conventional multi-input circuit described above, the present invention latches input signals of a plurality of interrupt input terminals by a plurality of latch circuits controlled by a clock signal. The difference is that even if the terminal states of two or more input terminals change at the same time, changes in the states of all input terminals can be detected by providing means for calculating the exclusive OR of the outputs of the input terminals.

[Means for solving problems]

The multi-input interrupt circuit of the present invention latches input signals of a plurality of input terminals with a plurality of latch circuits controlled by a clock output from a clock control circuit, takes an exclusive OR of the outputs of the plurality of latch circuits, and It has exclusive OR means for generating an interrupt signal.

[First example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a multi-input interrupt circuit according to a first embodiment of the present invention.

This circuit includes terminals A, B, C, and D, and a latch circuit 110.
120, 130, and 140, a clock control circuit 150, an exclusive OR circuit 160, an edge detection circuit 320, an interrupt flag 330, an input buffer 340, and an internal bus 350.

In FIG. 1, terminals A, B, C, and D, an edge detection circuit 320, an interrupt flag 330, an input buffer 340, and an internal bus 350 are the same as those shown in the conventional example, so their explanation will be omitted.

The latch circuits 110, 120, 130, 140 have terminals A
, B, C, and D are input, and the clock signal 11
This is a latch circuit that uses 1, 121, 131, and 141 as latch clocks and outputs latch outputs of 112° 122, 132, and 142.

The clock control circuit 150 includes latch circuits 110 and 120.
, 130, 140 are terminals A and B.

This is a clock control circuit that sequentially outputs clock signals 111, 121, 131, and 141 that determine the timing of latching the C and D terminal states.

The exclusive OR circuit 160 has latch outputs 112 and 122.
, 132, 142 as inputs, performs an exclusive OR, and outputs an exclusive OR signal 301.

Next, the operation of this embodiment will be explained.

FIG. 2 is a time chart showing the operation of this embodiment. Terminal A is at a high level, terminal B is at a low level, terminal C is at a high level, and when the terminals are kept at a low level, at timing t1, the terminal C becomes a high level. Then, at timing t2, terminal B changes from high level to low level, and furthermore, at timing t3, terminal A changes from high level to low level, and terminal B changes from low level to high level at the same time.

In the initial state, exclusive OR signal 301 is at low level. When the terminal C changes from high level to low level at timing t1, when the clock signal 131 is generated at the timing of ctl, the latch circuit 130 latches the input signal of the terminal C, and the latch output 132 changes from high level to low level. . The exclusive OR signal 301 becomes high level by the exclusive OR of the latch outputs 112, 122, 132, and 142, and the edge detection circuit 320 detects the rising edge of the exclusive OR signal 301 and outputs the set signal 302. output and set the interrupt flag 330.

The central processing unit starts interrupt processing, outputs a strobe signal 341 in the interrupt processing, and outputs a strobe signal 341 to the input buffer 340.
The input state of each terminal is output to the internal bus 350 via the internal bus 350 to determine the cause of the interrupt. The central processing unit uses internal bus 3
By reading the input state of each terminal outputted to 50, the terminal C whose state has changed can be identified, and processing corresponding to the change in the input of terminal C can be executed.

Next, when the terminal B changes from low level to high level at timing t2, the clock signal 1217'JSct
When this occurs at timing 2, the latch circuit 120 latches the input signal at terminal B, and the latch output 122 changes from low level to high level. The exclusive OR signal 301 becomes low level by the exclusive OR of the latch outputs 112, 122, 132, and 142, and the edge detection circuit 320
detects the falling edge of the exclusive OR signal 301,
A set signal 302 is output and an interrupt flag 330 is set. The central processing unit starts interrupt processing, outputs a strobe signal 341 in the interrupt processing, outputs the input state of each terminal to the internal bus 350 via the input buffer 340, and determines the cause of the interrupt. By reading the input status of each terminal output to the internal bus 350, the central processing unit can identify the terminal B whose status has changed, and executes processing corresponding to the input change of the terminal B.

Furthermore, if the terminal A changes from high level to low level and the terminal RI simultaneously changes from low level to high level at timing t3, when the clock signal 111 is generated at timing ct3, the latch circuit 110 latches the input signal of terminal A. However, the latch output 112 changes from high level to low level.

The exclusive OR signal 301 is the latch output 112°122
．． The edge detection circuit 320 detects the rising edge of the exclusive OR signal 301 and outputs a set signal 302.
Set interrupt flag 330. The central processing unit starts interrupt processing, and in the interrupt processing, strobe signal 3
41, the input state of each terminal is output to the internal bus 350 via the input buffer 340, and the cause of the interrupt is determined. By reading the input status of each terminal output to the internal bus 350, the central processing unit can identify the terminal A whose status has changed, and executes processing corresponding to the input change of the terminal A.

Next, when the clock signal 141 is generated at timing ct4, the latch circuit 140 latches the input state of the terminal, and the latch output 142 changes from low level to high level. The exclusive OR signal 301 is the latch output 112,
122, 132°142 becomes low level, and the edge detection circuit 320 receives the exclusive OR signal 3.
01 is detected, a set signal 302 is output, and an interrupt flag 330 is set. The central processing unit starts interrupt processing, outputs a strobe signal 341 in the interrupt processing, outputs the input state of each terminal to the internal bus 350 via the input buffer 340, and determines the cause of the interrupt. By reading the input state of each terminal output to the internal bus 350, the central processing unit can identify the terminal whose state has changed, and executes processing corresponding to the input change of the terminal.

As described above, by controlling the timing of latching each terminal state using the clock, even if the states of two or more of the multiple input terminals change simultaneously,
All pin states can be detected.

[Second example] FIG. 3 is a block diagram of a second embodiment of the invention.

This circuit consists of input terminals A, B, C, and D, and a latch circuit 11.
0, 120, 130, 140 and clock control circuit 2
30, exclusive OR circuit 160, and edge detection circuit 3
20, an interrupt flag 220, and an interrupt address generator 210.

In FIG. 3, input terminals A, B, C, D, latch circuits 110, 120, 130, 140, exclusive OR circuit 160)t are the same as those shown in the first embodiment, and , the edge detection circuit 320 is the same as that shown in the conventional example, so a description thereof will be omitted.

The interrupt flag 220 is set by the set signal 302.
A control signal 201 is output with a 1-bit interrupt flag set to 1'.

The interrupt flag 220 is cleared at the same time as the central processing unit starts interrupt processing.

The clock control circuit 230 sequentially outputs the clock signals 111, 121° 131.141 when the control signal 201 is 0°, and outputs the clock signals 111, 121° 131.141 when the control signal 201 is 1°. stop,
This is a clock control circuit.

The interrupt address generation section 210 outputs a latch output 112.1.
22, 132, 142 as input, each latch output 1
This is an interrupt address generation section that outputs an interrupt vector address signal 211 corresponding to the contents of 12, 122, 132, and 142.

Next, the operation of the second embodiment of the present invention will be explained.

FIG. 4 is a time chart showing the operation of this embodiment. When terminal A is at high level, terminal B is at low level, terminal C is at high level, and terminal RI is at low level, terminal A goes high at timing tlo. This shows the case where the level changes from low level to high level, and the terminal changes from low level to high level at the same time.

In the initial state, exclusive OR signal 301 is at low level. When terminal A changes from high level to low level and terminal A changes from low level to high level at timing tlo, the clock signal 111 changes at timing ctl.
When the signal is generated at O, the latch circuit 110 latches the input signal at the terminal A, and the latch output 112 changes from high level to low level. Further, the exclusive OR signal 301 becomes high level by the exclusive OR of the latch outputs 112, 122, 132, and 142, and the earth edge detection circuit 320 detects the rising edge of the exclusive OR signal 301 and outputs the set signal 302. is output and the interrupt flag 220 is set. By setting the interrupt flag 220, the control signal 201 becomes “
1', and the clock control circuit 230 stops outputting the next clock signal 121. Which latch circuit 11
The states of 0.120, 130, and 140 are also clock signal 1.
Since the outputs 11, 121, 131, and 141 are stopped, they do not change (section indicated as stl in the figure). The interrupt address generation unit 210 outputs an interrupt vector address signal 211 corresponding to the input of the terminal A whose state has changed. The central processing unit starts interrupt processing based on the interrupt vector address signal 211, and the interrupt flag 220 is cleared, so the control signal 201 becomes "Ol" and the clock control circuit 230 outputs the clock signal 121 again in order. However, it becomes possible to detect changes in terminal status.

Next, when the clock signal 141 is generated at timing ct20, the latch circuit 140 latches the input signal at the terminal, and the latch output 142 changes from low level to high level. Furthermore, the exclusive OR signal 301 is output from the latch output 112.
, 122, 132, and 142, the edge detection circuit 320 detects the falling edge of the exclusive OR signal 301, outputs a set signal 302, and sets the interrupt flag 220. By setting the interrupt flag 2200, the control signal 201 becomes 1', and the clock control circuit 230 outputs the next clock signal 111.
Stop outputting. Which latch circuit 110, 120
, 130, 140 also correspond to the clock signals 111, 12
1,131°141 Since the output is stopped, there is no change (section indicated as ct2 in the figure). The interrupt address generating section 210 outputs an interrupt vector address signal 211 corresponding to the input of the terminal whose state has changed.

The central processing unit starts interrupt processing based on the interrupt vector address signal 211, and the interrupt flag 220 is cleared, so the control signal 201 becomes "0" and the clock control circuit 230 starts processing the clock signal 111 again. output, allowing detection of changes in terminal status.

As shown in the second embodiment, since the output signal of the interrupt flag is fed back as a control signal to the clock control circuit, the interrupt processing is started even if the latch clock cycle is shorter than the startup time of the interrupt processing. During the period until
It is possible to suppress generation of an interrupt request due to the next latch output change.

In other words, even if two or more of multiple input pins change at the same time, a change in one pin will generate one interrupt request and the corresponding interrupt processing can be activated, and any change in any pin will be detected. can do.

Furthermore, by providing an interrupt address generation section that outputs an interrupt address signal corresponding to each terminal input, it becomes unnecessary to determine which terminal state has changed in the interrupt processing, and the interrupt processing time can be shortened.

〔Effect of the invention〕

As explained above, the present invention provides a multi-input interrupt circuit that includes a latch circuit, latches an input signal and outputs from the latch circuit under clock control, and generates an interrupt signal by exclusive OR of the latch outputs. Therefore, even if the states of two or more input terminals change simultaneously,
This has the effect of detecting changes in all terminal states.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a time chart showing the operation of the first embodiment, and FIG. 3 is a block diagram of a second embodiment of the present invention. , FIG. 4 is a tie chart showing the operation of the second embodiment, FIG. 5 is a block diagram of a conventional large power interrupt circuit, and FIG. 6 is a time chart showing the operation of the conventional example. 110.120,130,140”-・Latch circuit, 1
11,121,131,141...Clock signal, 112,122,132,142...Latch output signal, 150,230...Clock control circuit, 160,310... ...exclusive OR circuit,
320... Edge detection circuit, 220, 330.
...Interrupt flag, 340...Input buffer, 350...Internal bus, 201...
- Clock control signal, 211... Interrupt vector address signal, 301... Exclusive OR signal, 302... Set signal, 341...
Input strobe signal. Agent Patent Attorney Otohara Uchihara 2 Figure < o (,3Q $411!I

Claims (1)

[Claims] The multi-input interrupt circuit includes a plurality of interrupt input terminals, a plurality of latch circuits corresponding to the plurality of interrupt input terminals on a one-to-one basis, and a clock control circuit, and is controlled by a clock output from the clock control circuit. latching the input signals of the plurality of interrupt input terminals by the latch circuit, and generating an interrupt signal by the exclusive OR of the outputs of the plurality of latch circuits. Input interrupt circuit.