JPH01124258A - Bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To eliminate a need for an ion implantation process and a complicated process accompanied by the process and to freely regulate an intrinsic region by a method wherein an insulator layer provided to be adjacent to individual active layers is contained and an extraction electrode of an emitter layer and a collector layer is extended and formed on the insulator layer. CONSTITUTION:In an emitter-top HBT where a collector layer 2 composed of n-GaAs, a base layer 3 composed of p-GaAs and an emitter layer 4 composed of n-AlGaAs have been formed on a semiinsulating GaAs substrate 1, an emitter extraction electrode is provided in such a way that it is to be adjacent to an intrinsic region and that it is extended on an SiO2 layer 8 as an insulator formed selectively on the semiinsulating substrate. That is to say, because an emitterbase junction does not exist in a part other than the intrinsic region, a parasitic capacitance value is small and a high-speed high-frequency characteristic is improved. In addition, because an active layer can be laminated in a region partitioned by the insulator layer on the semiinsulating substrate by a selective epitaxial method, an ion implantation process and a complicated process accompanied by the process are not required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor and a method for manufacturing the same.

[Conventional technology]

In recent years, efforts have been made to increase the speed and integration of semiconductor devices.

Active research and development is underway. In particular, bipolar transistors (hereinafter referred to as HBTs) that utilize heterojunctions such as compound semiconductors are attracting attention as devices that can maintain high emitter injection efficiency even with base t-X doping and have high gain and high-speed performance. ing. This HBT has become possible due to advances in thin film multilayer process technology for compound semiconductors and single crystal insulators, such as molecular beam epitaxial growth, metal organic vapor phase epitaxy, and ion implantation technology. In order to achieve these characteristics, it is necessary to fully implement self-alignment and miniaturization of the device structure, as well as to eliminate parasitic parameters such as base-emitter parasitic junctions, base-collector parasitic junctions, and base resistance. For this purpose, an HBT having the structure shown in FIG. 3 has conventionally been used.

In the figure, a collector layer 2 made of n-GaAs and a base layer ff made of p-GaAs are formed on a substrate 1.
13.

Emitter #4 made of n-AlGaAs is successively formed. Reference numeral 6 denotes the intrinsic region of the transistor, where the transistor actually operates. As mentioned above and as follows, HBT
In order to increase the operating frequency, it is necessary to miniaturize this intrinsic region. Therefore, conventionally the third
As shown in the figure, a high resistance Tll7 is provided in a part of the region for forming the extraction electrode 44 of the emitter layer by selectively implanting ions from the surface side of the substrate into the region including the emitter layer, base layer, and collector layer. The ratio defines the intrinsic region.

[Problems that the invention helps solve]

In such a conventional HBT, the entire surface of the substrate is covered.

In order to ensure that the emitter layer, base layer, and collector layer face each other, an ion-implanted layer is provided to define the intrinsic region and eliminate parasitic junctions in regions other than that region.
Even with this ion-implanted layer, the parasitic capacitance can only be reduced by about 30 to 40%.

Furthermore, in order to completely form the ion implantation #, the next process step of protecting the intrinsic region during the high energy ion implantation step was also extremely complicated. For this reason, such conventional HBTs have the drawback of not being suitable for mass production and cost reduction.

An object of the present invention is to provide a bipolar transistor with a small parasitic capacitance, eliminate the need for an ion implantation step and the complicated process steps involved therewith, and allow the intrinsic region to be freely defined. An object of the present invention is to provide a method for manufacturing a bipolar transistor.

[Means for solving problems]

The bipolar transistor of the present invention has nine collector (or emitter) layers formed on a semi-insulating substrate and made of a first (or third) semiconductor material, and a second collector (or emitter) layer formed on this collector (or emitter) layer. a base layer made of a semiconductor material; and a third (or first) layer formed on the base layer.
), in which a part of the lead electrode of the emitter (or collector) layer of the transistor is formed on the half-R, Wik 9 substrate. or I
! It has a structure in which it extends over an insulator layer provided in contact with the side surface of each layer made of semiconductor material No. 3.

Further, the method for manufacturing a bipolar transistor of the present invention includes a step of forming an insulating layer of a predetermined thickness on a semi-insulating substrate;
selectively etching the insulating layer down to the insulating substrate using a first mask having a predetermined pattern; etching a first (
or a step of forming a collector (or emitter) layer made of a third) semiconductor material, a step of forming a 7-inch base made of a second semiconductor material on this collector (or emitter) layer, and a step of forming a 7-inch base made of a second semiconductor material on this collector (or emitter) layer; a step of forming an emitter (or collector) NII made of a third (or first) semiconductor material; and a second mask extending a region* including the boundary between the insulator layer and the emitter (or collector) layer. and a step of providing an emitter (or collector) extraction electrode on the extended portion.

[Effect]

The bipolar transistor of the present invention has an insulator layer provided in contact with each active layer, and the lead electrode of the emitter (or collector) layer is provided extending over the insulator layer. Base-emitter (or collector) parasitic capacitance is reduced. In addition, the method for manufacturing a bipolar transistor of the present invention includes forming active layers such as a base layer and an emitter layer of a transistor by selective epitaxial growth on the surface of a semi-insulating substrate partitioned by an insulating layer, and forming an emitter layer only in the intrinsic region. Finally, the parasitic base-emitter (or collector) junction can be eliminated without the need for ion implantation, since the NI (or collector) and base layers can be stacked together.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Figure 1 shows an example of an uninvented bipolar transistor)
It is a sectional view of an IBT chip. This example is a semi-insulating G
a Collector layer 2 made of n-GaAs on an As substrate l, a base layer 3 made of I)-Gaps. n-A
This is an emitter-top HBT in which emitter layers 4 made of IGaAs are formed intermittently. In this HBT, an emitter extraction electrode is an insulator that is selectively formed on a semi-insulating substrate in contact with an intrinsic region.
It is provided extending on the z layer 8.

Unlike conventional ion-implanted layers, there is no junction in this part.

FIGS. 2(a) to 2(a) are cross-sectional views of a ninth semiconductor chip shown in the order of the ninth process for explaining an embodiment of the method for manufacturing an uninvented bipolar transistor.

First, as shown in FIG. 2(a), an insulating layer 8t made of, for example, 5i02 is formed on a semi-insulating GaAs substrate 1 to a thickness of about soon m.

Then, using a mask with a predetermined (turn) as shown in FIG.
Selective etching is performed until the substrate is reached.

Next, as shown in FIG. 2 (CJ), the S i Oz
5 thickness each by MOCVD method or atomic layer epitaxy (ALE) method using rfj as a mask.
A collector layer 2 made of n-GaAs with a thickness of about 1,100 nm, a base 13 made of p-GaAs with a thickness of about 1100 nm, and an emitter layer 4 made of n-AJGaAs with a thickness of about 200 nm are formed.

Next, as shown in FIG. 2 (dl), at least 5i0
A u G e -N i -A u
An emitter lead electrode 44 is formed.

Finally, the base layer and the collector layer are partially exposed using a mask having a predetermined pattern using a well-known method to form a base extraction electrode 33 made of AuZn and a collector extraction electrode 2 made of AuGe-Ni-Au, respectively.
2, the HBT shown in FIG. 1 can be obtained.

There is no need to explain in detail that in the above embodiments, the emitter layer and the collector layer may be replaced.

〔Effect of the invention〕

As explained above, in the bipolar transistor of the present invention,
Since the insulator layer is provided in contact with the active 9111 surface, there is no emitter (or collector)/base junction other than the intrinsic region, which has the effect of reducing parasitic capacitance and improving high speed and high frequency characteristics. In addition, the method for manufacturing a bipolar transistor of the present invention allows the active layer to be formed by selective epitaxial method in a region defined by an insulating layer of a semi-insulating substrate, thereby eliminating the need for an ion implantation step and the complicated process steps involved. It has the effect of realizing mass production and cost reduction of bipolar transistors, which have excellent high-speed and high-frequency characteristics, and can be freely specified without any intrinsic type*.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of an HBT chip showing an embodiment of an uninvented bipolar transistor, and Figs. 2 (al to d) are arranged in the order of steps to fully explain an embodiment of a method for manufacturing an uninvented bipolar transistor. Cross-sectional view of a semiconductor chip. FIG. 3 is a cross-sectional view of an example of a conventional bipolar transistor. 1...Semi-insulating GaAs substrate, 2...n
GaAs collector layer, 3.-p-GaAa base layer,
4-.n-AIUaAs, c-mitter layer, 6... Intrinsic region of transistor, 7... Ion implantation layer, 8...
5iOz layer, 15... photoresist mask, 22.
・・AuGe-Ni-Au collector extraction electrode, 33・
...AuZn base extraction electrode, 44...A u G
e -N i -A u emitter extraction electrode. Agent Patent Attorney Susumu Uchihara%1m Figure 2 Figure 2

Claims (2)

[Claims] (1) A collector (or emitter) layer made of a first (or third) semiconductor material formed on a semi-insulating substrate, and a second semiconductor material formed on this collector (or emitter) layer. and an emitter (or collector) layer formed on the base layer and made of a third (or first) semiconductor material, wherein the emitter (or collector) layer of the transistor has a A part of the extraction electrode is provided extending over an insulating layer provided on the semi-insulating substrate in contact with a side surface of each layer made of the first to third semiconductor materials. bipolar transistor. (2) forming an insulating layer of a predetermined thickness on a semi-insulating substrate, and selecting the insulating layer until it reaches the semi-insulating substrate using a first mask having a predetermined pattern; forming a collector (or emitter) layer made of a first or third semiconductor material on the exposed semi-insulating substrate; and forming a second collector (or emitter) layer on the collector (or emitter) layer. a step of forming a base layer made of a semiconductor material, a step of forming an emitter (or collector) layer made of a third (or first) semiconductor material on this base layer, and a step of forming a base layer made of a third (or first) semiconductor material; collector)
forming a second mask exposing a region including the boundary with the layer, and forming an emitter (or collector) in the exposed portion;
1. A method for manufacturing a bipolar transistor, comprising the step of providing an extraction electrode.