JPH01129823U - - Google Patents
Info
- Publication number
- JPH01129823U JPH01129823U JP2422288U JP2422288U JPH01129823U JP H01129823 U JPH01129823 U JP H01129823U JP 2422288 U JP2422288 U JP 2422288U JP 2422288 U JP2422288 U JP 2422288U JP H01129823 U JPH01129823 U JP H01129823U
- Authority
- JP
- Japan
- Prior art keywords
- alignment mark
- device pattern
- flat part
- pattern formed
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000013039 cover film Substances 0.000 description 1
Description
第１図は本考案に係る半導体装置の一実施例を
示す断面図、第２図ａ〜ｉはその製造工程を説明
する断面図、第３図ａ〜ｆは従来の半導体装置の
製造工程を説明する断面図、第４図ａ〜ｄは別の
従来の半導体装置の製造工程を説明する断面図で
ある。
１１：半導体基板、１２：第１のデバイスパタ
ーン、１３：位置合わせマーク、１３ａ：突起部
、１３ｂ：平坦部、１６：カバー膜、１９：第２
のデバイスパターン。
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, FIGS. 2 a to i are sectional views explaining the manufacturing process thereof, and FIGS. 3 a to f are sectional views showing the manufacturing process of a conventional semiconductor device. Cross-sectional views to be explained, FIGS. 4A to 4D are cross-sectional views to explain another conventional manufacturing process of a semiconductor device. 11: Semiconductor substrate, 12: First device pattern, 13: Alignment mark, 13a: Projection, 13b: Flat part, 16: Cover film, 19: Second
device pattern.
Claims (1)
れ形成される第１のデバイスパターンおよび位置
合せマークを有している第１のパターンと、前記
位置合わせマークを位置決め基準として前記第１
のデバイスパターンの領域に形成される第２のデ
バイスパターンとを備えている半導体装置におい
て、 前記位置合わせマークは、前記下層膜の平坦部
とこの上面から突出する突起部とから成ることを
特徴とする半導体装置。[Claims for Utility Model Registration] A first device pattern formed by etching a lower layer film on a semiconductor substrate, and a first pattern having an alignment mark, using the alignment mark as a positioning reference. Said first
and a second device pattern formed in a region of the device pattern, wherein the alignment mark is comprised of a flat part of the lower film and a protrusion protruding from the upper surface of the flat part. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2422288U JPH01129823U (en) | 1988-02-25 | 1988-02-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2422288U JPH01129823U (en) | 1988-02-25 | 1988-02-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01129823U true JPH01129823U (en) | 1989-09-04 |
Family
ID=31243890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2422288U Pending JPH01129823U (en) | 1988-02-25 | 1988-02-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01129823U (en) |
-
1988
- 1988-02-25 JP JP2422288U patent/JPH01129823U/ja active Pending