JPH01136248A - Fault detecting and switching device - Google Patents

Abstract

PURPOSE:To detect the fault of a processor without using a fault detecting line by providing a fault detecting memory in transmission processing part, and monitoring the presence/absence of the state change of data at a constant cycle. CONSTITUTION:As for input/output data to a process, the address of the transmission processing parts TP11-TPF1 and data are transmitted to transmission paths TL1 and TL2 by a prescribed procedure only when state change occurs at an interval of around 10-200ms. And for check data for detecting the fault in the fault detecting memory part of a RAM 23, the data of [0, 1] is rewritten to the data of [1, 0] at a cycle of 200-400ms, and it is transmitted with the address according to the above stated data transmission. The check data for detecting the fault to be transmitted is monitored by each CPU for a constant time. As a result, if the processor in which no change occurs in the check data for detecting the fault exists out of the processors 1-F, it is decided that abnormality is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to a failure detection switching device that detects a failure in an information processing device and prevents the failure from spreading to other processing devices.

80 Summary of the Invention This invention provides a fault detection switching device in which a fault detection memory is provided in the processing device and a fault in the processing device is detected from the contents of this memory, thereby preventing a fault in one processing device from spreading to the entire system. It is intended to do so.

C0 Conventional technology Figure 6 is an explanatory diagram of the configuration of a conventional information processing system.
P is a processing device, and each processing device l to F has two main processing units M P ll-M P F I and a transmission processing unit TPt+
- Consists of TPFI. The main processing units M P r r and M P + * of the processing device l are CPU 1
1.12, the transmission processing unit T P ++ , T
P1m is composed of CPUll1.112 and CPU121,122. Main processing unit MPFI of processing device F.

M'PFI consists of CPUFl and F2, and transmission processing units TPF, TP□ are CPUFII, F'12 and F21.
, F22. In addition, the number r attached to the CPU
lllJ, rl12J, . . . are address names. T.L.
,, TL is a transmission path, and this transmission path TLl has a CPU 111.1 of a transmission processing unit T P ll"'-T P v*.
21 to CPUFI l, F21 are connected, and the transmission line TL
, the CPU 11 of the transmission processing unit TPr~TP□
2,122~CPUF12. F22 is connected. FD
is a failure detection line for detecting a failure in the processing device 1-F, and this detection line FD is connected to the transmission processing unit T P of each processing bag ril-F.
It is connected to the input/output section I10 of t+ to TP□.

The processing devices 1 to F configured as described above receive information from an interface (not shown), process this information, and transmit the processed information to the transmission lines TL, , 'rt, and t. When the processing device 1-F is processing information, each processing device 1
-F, the failure is detected and processed as necessary between the respective devices via the input/output section (shown in FIGS. 7 and 8) via the failure detection line FD.

FIG. 7 is a block diagram showing details of the CPUI 1 f of the transmission processing unit TPII, in which 71 is the CPU, 72 is the memory, and 7
3 is a failure detection hardware section, 74 is a transmission interface, and 75 is a peripheral input/output section, which are connected to an internal bus 76. The transmission interface 74 is a transmission line T
The surrounding person output section 75 is connected to the failure detection line FD. In FIG. 7, when the self-device becomes abnormal, a failure detection hardware section 73 detects this abnormality and issues a top priority interrupt to the CPU 71 to detect the failure.

D1 Problems to be Solved by the Invention The above means is for the self-device, but when an abnormality occurs in another device, an interrupt is generated as shown in FIG. 8 to detect the failure. Figure 8 shows the transmission processing unit TP++
A block diagram showing details of CPUI 11 and 112 of
The same parts as in FIG. 7 are indicated with the same reference numerals. This eighth
In the figure, contact amplifiers 77 and 78 are provided to monitor abnormalities in other devices. As shown in Figure 8, the failure detection lines FD,, FD, (this F D 1. F D
* indicates a bundle of failure detection lines FD shown in FIG. ing. Therefore, since the failure detection line FD becomes a common part of the system, there is a problem in that if the failure detection line in the common part fails, the failure spreads to the entire system.

Means for Solving Problem E8 This invention relates to a data transmission device in which information from a process etc. is processed by a processing device and transmitted to a transmission path, and information on the transmission path is transmitted to the process etc. via the processing device. , A failure detection memory section that transmits information from each processing device at a predetermined period through a transmission path and periodically rewrites the contents of the memory provided in each processing device at a period slightly longer than the above period is installed in all processing devices. The system monitors changes in the state of data in this memory section at regular intervals, detects a faulty processing device based on the presence or absence of a change in the state of data in the memory section, and determines whether the processing device is faulty or healthy. This system is characterized in that it performs the following steps to switch to a healthy processing device.

The F0 action failure detection memory section periodically rewrites data at bit positions assigned to each processing device.

The contents of the memory edict will not change the status quo data, but only the data whose state has changed will be rewritten.

This data change is performed periodically, the data is monitored for a certain period of time, and a processing device whose state does not change is considered to be faulty.

G. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same parts as in FIG. 6 are denoted by the same reference numerals.

In FIG. 1, transmission processing units TP, ~
TPFI and T P +t ~ T P vt (7) C
P Ull, 112~CPUFII, F'l12 and c
pU121.122 to CPUF21. F22 is transmission line T
A transmission processing unit TP++ is connected to L,,TLt.

~TP□tTPtt-TPvt is provided with a failure detection memory section as described later. FIG. 2 is a configuration explanatory diagram showing details of the transmission processing unit T P r + shown in FIG. In addition to the failure detection memory section (2 bits), this RAM 23 contains data (detection data) that each processing device inputs and outputs to and from the target plant.

It is equipped with a memory section for (control data). 24 is the transmission line T
25 is a transmission interface for data transmission between Lt and transmission processing unit TP; 25 is main processing unit MPr;
+ and transmission processing unit TP1. 26 is an interface for transmitting data between processes and the like.

The failure detection memory section of the RAM 23 contains 2 bits (0, 1) or (, 1, 0) as check data for failure detection.
Either one is stored in memory. Check data for failure detection is stored in memory corresponding to the address of each transmission processing section. FIG. 3 shows the state of this memory. In Figure 3, the number riz''.

r121J... is the address name of the CPU.

In the embodiment configured as described above, the input/output data to the process is performed by changing the addresses and data of the transmission processing units TPl+ to TPrt according to the determined transmission procedure only when there is a change in status at intervals of about 10 to 200 iS. Transmission line TL, TL,
to be transmitted. On the other hand, the failure detection check data in the failure detection memory section of the RAM 23 is rewritten from [o, i) data to (1, 0) data at a cycle of 200 to 40011S, and is performed in conjunction with the above data transmission. , transmitted along with the address. This transmitted failure detection check data is monitored by each CPU for a certain period of time (for example, 1 second). As a result of this monitoring, the check data for fault detection is [0, 1].
If there is a processing device 1-F that does not change from (1, 0), it is considered that an abnormality has occurred.

A device that detects an abnormality, that is, no change in the state of check data for failure detection, will be described below by taking the processing device 1 as an example.

(a) Memory address rlllJ, r121J - Check data change (b) Memory address rl12J, r122J -> Check data change If (a) or (b) above means that the transmission line TL is defective, this defect At this time, the transmission line TL is switched to the transmission line TL for data transmission.

(c) Memory addresses rllllJ, rl12J → Check data unchanged (d) Memory addresses r121J, r122J → Check data change If (c) or (d) above means that the transmission processing unit TP is defective, this defect When this happens, switching to the normal CPU side is performed.

(e) Memory addresses rtllJ, r121J → Check data unchanged (f) Memory addresses rl12J, r122J → Check data changed If (e) and (f) above, main processing unit M P + +
This means that the main processing unit MP, . Exclude from TLt. The recovery process starts from the time when the failure detection memory section starts rewriting data normally.
After monitoring for seconds, each processing device determines that it has returned to normal, and is able to switch to recovery.

The above is an example of the case of processing device 1, but each processing device 1-
Abnormality of the transmission path in F is determined by the lowest address bit rxxl/2J (1/2 means ! or 2), and abnormality determination by the transmission processing section is determined by the middle of the address bit rxl/2
In xJ (1/2 means 1 or 2), the abnormality judgment of the main processing section is based on the most significant address bit rl/FXXj (
1/F means 1 to F), and processing can be performed according to the detected abnormality.

The flowchart in FIG. 4 is for checking the contents of the failure detection memory section, and step S is for checking the contents of the failure detection memory section.

is a processing unit that specifies the address of the failure detection memory,
The address is the entire address or the address of the device required by the own device. Step S.

performs the process of reading the check data in the memory. After reading the data in step S, the previous check data and the current check data are compared in step S3 to determine whether the bit is inverted or not. to decide. If it is determined that the image is reversed as a result of the determination, the process advances to step S4, and returns to the beginning after a certain period of time. When it is determined in step S3 that the image has not been reversed, the process in step S is performed. In step S, it is determined whether there is an abnormality in the device (or transmission path) associated with the address corresponding to the failure detection memory. Thereafter, in the process of step S6, the process returns to the beginning at a certain time.

Fifth step is to periodically rewrite the contents of the failure detection memory section.
This is done based on the following flowchart shown in the figure. Step S1 is a processing unit that specifies the address of the failure detection memory, and if the address is specified in step SI, the process moves to step St for writing data. Step S
, if the data has been written, the process proceeds to step S3. In step S3, it is determined whether a certain period of time has elapsed since the data was written into the memory, and if the certain period of time has elapsed, the process moves to step S4.

If a certain period of time has elapsed in step S3, this process is repeated until the certain period of time has elapsed.

Step S4 is a processing unit that specifies the address of the failure detection memory. If the address is specified in step S4, the process moves to writing the data in step S, and the data rO, IJ written in step S is , rewritten as OJ. In step S5, it is determined whether a certain period of time has elapsed in step S8 since the data in the memory was rewritten. If it has elapsed, the process returns to the beginning, and if it has not elapsed, the process in step Sll is performed until the elapsed time.

In the above embodiment, transmission line data is transmitted and received using the token system shown in FIG. In FIG. 9, node A receives a token (transmission right) for the indicated data in the format shown in FIG. 10(a). Packet data (including data in the fault detection memory) shown in the format of FIG. 1O(b) is sent from node A to node B. Or it is sent from node A to all nodes. When data transmission to node B is completed, a data token shown in the format shown in FIG. 1.theta.(a) is passed to node C.

Repeat the steps in Figure 9 below.

H6 Effects of the invention As described above, according to the invention, a failure detection memory section is provided in the transmission processing section, changes in the state of data in this memory section are monitored at regular intervals, and whether or not there is a change in the state of the data is detected. Since a failure is detected by the following, it is possible to eliminate the need for a failure detection line and improve the reliability of the processing device.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a schematic configuration showing one embodiment of the present invention, FIG. 2 is an explanatory diagram of a configuration showing details of the main parts of the invention, and FIG. 3 is an explanatory diagram showing a data arrangement state of a failure detection memory section. , FIG. 4 and FIG. 5 are flowcharts, FIG. 6 is an explanatory diagram showing the configuration of a conventional example, FIGS. 7 and 8 are explanatory diagrams showing details of the transmission processing section, and FIG. 9 is an explanation of the token method. Figures 1.theta.(a) and (b) are explanatory diagrams showing the format. MP Il, MP t*... Main processing section, T P
t+. TP,...Transmission processing section, TL,,TLt...Transmission line, 1-F...Processing device, 23...RAM0 Fig. 1 1 device [Fig. 2 Fig. 9 A\ -l daa'7 ahead\・I9゛≧Ig ahead, Fukutoy S Riki ball, In name shikoi mesoichi'I old J grass'fA food +g gori saikan 8ni

Claims (1)

[Claims] (1) In a data transmission device that processes information from a process, etc. using a processing device and transmits it to a transmission path, and also transmits information on the transmission path to the process, etc. via the processing device, a predetermined cycle is transmitted through the transmission path. All processing devices are equipped with a failure detection memory section that transmits information from each processing device and periodically rewrites the contents of the memory provided in each processing device at a period slightly longer than the above-mentioned period. Monitors state changes at regular intervals, detects a faulty processing device based on the presence or absence of a state change in the data in the memory, determines whether the processing device is faulty or healthy, and switches to a healthy processing device. A failure detection switching device characterized by performing the following.