JPH01140367A - Memory coupling type multiprocessor system - Google Patents

Abstract

PURPOSE:To perform inter-processor communication in parallel without generating dead lock by performing communication by checking the state of a lock area and registering a communication state on a lock byte when the communication is available. CONSTITUTION:The title system is constituted in such a way that four processors 1-4 are coupled via a memory 5. And plural communication areas 51 and 52, and the lock area 53 where the communication states of the processors 1-4 and the activity states of the communication areas 51 and 52 are displayed are provided in the memory 5, and the communication is performed by checking the state of the lock area 53 and registering the communication state of the lock byte in a state where the communication is available. In such a way, it is possible to perform the inter-processor communication in parallel without generating the dead lock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory-coupled multiprocessor system in which communication between processors is performed by exclusive control via memory.

[Conventional technology]

As a means of increasing the speed of computing, information processing devices have been made multi-processor. Conventionally, in the multi-processor system of this scale, when communication between Brosseners was performed, a lock area was set up corresponding to the communication area used for communication, the lock byte was checked, and if the lock byte was in an unlocked state, , the sender takes the lock using exclusive control that locks the lock byte and executes the test and set command to report the result, sends the necessary information to the receiver using the communication area, and the communication ends. At that point, the unlock command was executed to release the lock.

[Problem that the invention seeks to solve]

In the conventional multiprocessor system described above, when there are four or more processors, if a specific processor locks the lock byte for inter-processor communication, processors unrelated to that communication attempt to communicate with each other. Even if you do this, it has the disadvantage that it remains in a holding state without being executed.

In order to solve this problem, it has been considered to create multiple communication areas to enable communication between multiple sets of processors at the same time, but in this case, with conventional locks that support communication areas, This was not implemented due to the risk of the system deadlocking.

[Means for solving problems]

In the memory-coupled multiprocessor system of the present invention, the memory has a plurality of communication areas for inter-processor communication, and bits corresponding to each of the plurality of processors and the plurality of communication areas, and each processor is in a communication state. and a lock area that displays whether each communication area is in use.When each processor attempts to communicate, it checks the lock area and determines whether it and the other processor are inactive. communication state, and when any of the communication areas is in actual use, the communication state is exclusively registered in the locked area so that communication is performed via any communication area that is in non-use. It has means for performing post-communication and canceling the exclusive registration upon completion of the communication.

[Effect]

Set up a lock area in memory that displays multiple communication areas, the communication status of multiple processors, and the usage status of multiple communication areas, check the status of the lock area, and when communication is possible, lock byte communication status Since it registers and communicates, it is possible to communicate between processors in parallel without causing deadlock.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the memory-coupled multiprocessor system of the present invention, and FIG. 2 does not show the relationship between the shoulder line around the mask register 11 in the processor 1 in FIG. 1 and the memory 5. It is a diagram.

This memory-coupled multiprocessor system has a configuration in which four processors 1.2.3.4 are coupled via a memory 2, and the memory 2 includes communication areas 51.
52 and a lock area 53 are allocated, and the processors 1 to 4 are provided with mask registers 11, 21, 31, and 41, respectively. Lock area 53 and mask registers 11.21.31.41 all have the same configuration; the first bit is processor 1, the second bit is processor 2, the third bit is processor 3, and the fourth bit is processor 4, processor 2. The 5th bit corresponds to the communication area 51, and the 6th bit corresponds to the communication area 52, and when it is "1", it indicates the locked state, and when it is MOH, it indicates the unlocked state. Here, the locked state means that the processor is in a communication state and the communication area is in a use state.

Referring to FIG. 2, around the mask register 11,
A NOT circuit 12, an AND circuit 13, 14, an OR circuit 15, 16, and a selector 17, 18 are connected to the signal line 101.
, 102, 103, 104, 105 and other signal lines, and a memory write register 54 (not shown in FIG. 1) is provided between the memory 5 and the signal line 102. There is. In FIG. 2, in order to avoid complexity, only a component that handles 1 bit of the 6-bit signal handled by the mask register 11 and memory 5 is shown.

The selector 17 is the mask register 1 of the lock area 53.
When at least bl of the bits designated by 1 are in the locked state, the memory 5 is selected, and when all are in the unlocked state, the AND circuit 15 is selected and output to the selector 18.

When the instruction is a test andlet instruction, the selector 18 selects the selector 17 and sets the memory write register 54 that corrupts data in the lock area 53 during the same read/write cycle for the memory 5, and when the instruction is unloaded. In the case of a lock instruction, the AND circuit 13 is selected and the bit designated by the mask register 11 in the lock area 53 is reset. Signal lines 101, 103, 104, 105
are both connected to a control section (not shown) within the processor 1. The signal line 101 connects to the communication area 51
．． 52, lock area 53, and other areas. The signal line 103 inputs a mask bit to the mask register 11. The signal line 104 inputs a signal indicating the type of instruction to the selector 18. A line 105 is a signal line through which the OR circuit 16 outputs the test results of the TEST1 to ANDSET commands.

Next, the operation of this embodiment will be explained.

When processor 1 attempts to communicate with processor 2,
Processor 1 sets the first, second, and fifth bits of mask register 11 corresponding to processor 1, processor 2, and communication area 51 to "1", and sets the other bits to IIOII. Subsequently, processor 1 executes a test and set instruction. [If all bits in the cock area 53 are “0”, the des1-and-set instruction is not executed. Then, the first, second, and fifth bits of the lock area 53 are set to “1” The other bits retain their previous value "0".

In this state, when the processor 3 and the block setter 4 try to perform processor communication, the processor 3 sets the third, fourth, and fifth bits of the mask register 31 to ll 1 II, and The bit is O''. Next, when the test (~and hit instruction) is executed, the test and hit instruction fails because the fifth bit of the lock area 53 is already 1''. Set the 3rd bit, 4th bit h, and 6th bit to “1pa”, and set the other bits to “
OII and execute the test and set instruction again, the test and set instruction is successful and the lock controller side Noah 5
The third, fourth, and sixth bits of 3 are set. As a result, processor-1 and processor-2 use the communication area 51, and the processor-1 and processor-2 use the communication area 51. 1) The three processors 4 can use the communication area 52 to simultaneously perform inter-processor communication. In this way, when the test and set command fails, the mask bits for the communication areas 51 and 52 are changed and the test and set command is executed again. By repeating this, when communication is busy, for example, processor 1 During the communication of processor 2, Brosets 1 and 3 are bu[1L! If there is a communication request for Tree 2, etc.
The processor 3 enters the samurai state while repeating the test and set command, and 01 and other control is realized.

Next, the detailed operation of the processor 1 will be explained with reference to FIG.

When the test and set instruction is executed, the f-ta of the lock area 53 is output from the memory 5.

This data is transferred to the mask register 1 by the AND circuit 14.
An AND operation is performed for each bit corresponding to the value of 1, and the OR circuit 16 performs an AND operation on all bits of the output.

When the output of the OR circuit 16 is 1'', at least one of the bits in the lock area 53 specified by the mask register 11 is in the [1] state. is output as is to the selector 18 and written to the [1] area 53 again, so each bit of the lock area 53 does not change.On the other hand, when the output of the OR circuit 16 is "0", the bits of the lock area 53 Mask register 11 with pin 1~
Since all the bits specified by are in the unlocked state, the ΔA circuit 15 sets these specified bits to “
1'', unspecified bits are input to the selector 17 without change, and new data is input to the lock area 53 via the selector 18.

When unlocking the lock area 53 after communication ends, the processor 1 executes an unlock instruction to reset the bits of the lock area 53 specified by the mask register 11 within the same write/read cycle. Sunawa 15,
The value of the lock area 53 output from the memory 5 and the value of the mask register 11 inverted by the NOT circuit 12 are ANDed for each corresponding bit by the AND circuit 13, and the output is sent to the selector. 18, the data is written to the lock area 53 again via the memory write register 54. In this case, the bit specified by the mask register 11 is inverted and becomes "0", so the corresponding bit in the lock area 53 is reset, and the unspecified bit is inverted and becomes "1°". Theory I!! Since the product is taken, the same value is written to the lock area 53 again without changing.

〔Effect of the invention〕

As explained above, the present invention sets a plurality of communication areas in a memory, a lock area that displays the communication status of a plurality of processors, and a usage status of the plurality of communication areas, checks the status of the lock area, and performs communication. By recording the communication status in the lock byte when possible, communication between processors can be carried out in parallel without causing deadlock.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the memory-coupled multiprocessor system of the present invention, and FIG. 2 is a configuration showing the relationship between the peripheral details of the mask register 11 in the processor 1 of FIG. 1 and the memory 5. It is a diagram. 1.2.3.4... Processor, 11.21, 31.41... Mask register, 5...
・Memory, 51.52...Communication area, 53...Lock area.

Claims (1)

[Claims] In a memory-coupled multiprocessor system that includes four or more processors and in which inter-processor communication is performed by exclusive control via memory, the memory has multiple communication areas for inter-processor communication. , having bits corresponding to each of the plurality of processors and the plurality of communication areas, and determining whether each processor is in a communication state;
and a lock area that displays whether each communication area is in use, and when each processor attempts to communicate, it checks the lock area and determines whether the processor itself and the other processor are in a non-communicative state; When any of the communication areas is in an unused state, the communication state is exclusively registered in the locked area so that communication is performed via any of the communication areas that are in an unused state, and then the communication is performed, A memory-coupled multiprocessor system comprising means for canceling the exclusive registration upon completion of the communication.