JPH01143251A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the discrepancy between the delay times of respective clock signal wirings and avoid the variation of the delay times of the clock signals by a method wherein the application length ratio of a high resistivity wiring whose unit length resistance is high and a low resistivity wiring whose unit length resistance is low is adjusted in accordance with the length of the clock signal wiring. CONSTITUTION:For a flip-flop 4 whose wiring length is long, the ratio of a low resistivity clock wiring 7 in the wiring is large and the length of the high resistivity clock wiring 6 is short. For flip-flop 5 whose wiring length is short, the ratio of a high resistivity clock wiring 9 in the wiring is large and the length of the low resistivity clock wiring 8 is short. By adjusting the wiring resistance like this, the variation of the delay times of the clock signals can be avoided. As the more low resistivity clock wiring is employed when the clock wiring is long and the more high resistivity clock wiring is employed when the wiring length is short, the variation of the delay time can be reduced easily and the operation of the flip-flop can be stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION 'Industrial Application Field' The present invention relates to a semiconductor device, and particularly to a semiconductor device such as a frisible flop having a clock wiring.

[Conventional technology]

Conventionally, clock wiring connected to a plurality of flip-flops housed in a semiconductor device has been arranged as shown in FIG. That is, this semiconductor chip 1. Flip-flops 4, 5 and a clock input terminal 2 are provided above the flip-flops 4, 5, and the input terminal 2 is connected to each flip-flop 4, 5 by a common lock wiring 3 and individual wirings 21-24. The individual wiring includes a high resistivity clock wiring 21 and a low resistivity clock wiring 22 for the flip-flop 4.
Accordingly, the low resistivity clock wiring 23 and the low resistivity clock wiring 24 are used for the flip-flop 5,
Each wire length was different.

[Problem that the invention seeks to solve]

The above-mentioned conventional semiconductor device has the disadvantage that the delay time of the clock signal varies widely due to the difference in the length of the clock wiring used to distribute the clock signal to the multiple flip-flops, making the operation of the flip-flops unstable. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that solves such problems and eliminates variations in clock signal delay times due to differences in clock wiring lengths to a plurality of flip-flops.

[Means for solving problems]

The configuration of the present invention provides a semiconductor device including a circuit in which a plurality of flip-flops are connected to a clock input terminal by a plurality of clock signal wirings, in which each of the clock signal wirings has a high resistance value per unit line length. Resistivity wiring and Ji
By AVing the usage ratio of low-resistivity wiring with a low resistance value per length in accordance with the length of each clock signal wiring, the deviation in delay time of each clock signal wiring can be reduced. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic layout diagram of the surface of a semiconductor device according to an embodiment of the present invention viewed from above. Semiconductor device chip 1
external clock input terminal 2, common lock wiring 3. Flip crop 4°5, high resistivity clock wiring with high resistance value per unit length 6,9. Low resistivity clock wiring lines 7 and 8 having a low resistance value per unit length are provided.

Flip-flops 4 with longer clock wiring lengths are wired with a larger proportion of low-resistivity clock wirings 7 and fewer high-resistivity clock wirings 6. Furthermore, in the flip-flop 5 whose clock wiring length is shortened, the ratio of the high-resistivity clock wiring 9 is increased and the low-resistivity clock wiring 8 is shortened. By adjusting the wiring resistance in this way, it is possible to eliminate variations in the delay time of Klong Kui No. 8.

FIG. 2 is a schematic layout diagram of the surface of a semiconductor device according to a second embodiment of the present invention, viewed from above. In this embodiment, two clock input terminals 12.1 are provided on a chip 1 of a semiconductor device.
High resistivity clock wiring 1 from 3 to flip-flop 14
5.17 and low resistivity clock wiring 16.18.

Flip-flop 14 that uses two systems of clock signals
is the low resistivity clock wiring 15 from the clock input terminal 12.
, are connected by high resistivity clock wiring 16, and are connected from clock input terminal 13 to low resistivity clock wiring 17 and high resistivity clock wiring 18. Clock input terminal 1
Since the clock wiring from 2 is shorter than that from the clock input terminal 13, the ratio of the high-resistivity clock wiring 15 is increased and the ratio of the low-resistivity clock wiring 16 is increased to increase the usage ratio of the low-resistivity clock wiring 17. The timing of the clock signal is adjusted by using less.

〔Effect of the invention〕

As explained above, the present invention uses many low-resistivity clock lines when the clock line length is long, in order to reduce the variation in delay time due to differences in the length of the clock lines to multiple flip-flops. When the wiring length is short, many high-resistivity clock wirings are used, so variations in delay time can be easily reduced and the operation of the flip-flop can be stabilized.

[Brief explanation of the drawing]

FIG. 1 is a schematic layout diagram of a semiconductor device according to a first embodiment of the present invention viewed from the surface, FIG. 2 is a similar layout diagram of a second embodiment of the present invention, and FIG. 3 is a diagram of a conventional semiconductor device. FIG. 2 is a schematic layout diagram of the device viewed from the front. 1... Semiconductor device chip, 2, 12.13... External clock input terminal, 3... Common lock wiring,
4,5.14...Flip-flop, 6,9°15.
17, 21. 24...High resistivity clock wiring, 7, 8
, 16, 18, 22. 23...Low resistivity clock wiring.

Claims (1)

[Claims] In a semiconductor device including a circuit in which a plurality of flip-flops are connected to a clock input terminal by a plurality of clock signal wirings, each of the clock signal wirings is connected to a high resistivity wiring having a high resistance value per unit line length. A semiconductor device characterized in that the difference in delay time of each of these clock signal wirings is reduced by adjusting the ratio of use of low resistivity wiring with a low resistance value in accordance with the length of each clock signal wiring. .