JPS6282807A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS6282807A JPS6282807A JP22413885A JP22413885A JPS6282807A JP S6282807 A JPS6282807 A JP S6282807A JP 22413885 A JP22413885 A JP 22413885A JP 22413885 A JP22413885 A JP 22413885A JP S6282807 A JPS6282807 A JP S6282807A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- integrated circuit
- package
- resistance value
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 27
- 238000010586 diagram Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、入力回路が所定の特性インピーダンスの伝送
路で構成された高速動作用の集積回路に関する。特に、
その伝送路の終端抵抗の実装に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit for high-speed operation in which an input circuit is constituted by a transmission line having a predetermined characteristic impedance. especially,
This paper relates to the implementation of the terminating resistor of the transmission line.
入力回路が所定の特性インピーダンスの伝送路で構成さ
れ、入力回路の反射を小さくした集積回路において、
集積回路パッケージ内にこの伝送路の終端抵抗を設けて
おき、さらにパフケージ外にこの伝送路に外付の抵抗を
接続して、二つの抵抗の並列抵抗値がその特性インピー
ダンスに近似する構成とすることにより、
終端抵抗の値のずれにより生じる反射を小さくしたもの
である。In an integrated circuit where the input circuit consists of a transmission line with a predetermined characteristic impedance and the reflection of the input circuit is reduced, a terminating resistor for this transmission line is provided inside the integrated circuit package, and an external terminal is provided for this transmission line outside the puff cage. By connecting additional resistors and creating a configuration in which the parallel resistance value of the two resistors approximates their characteristic impedance, reflections caused by differences in the values of the terminating resistors are reduced.
従来、第2図のように集積回路1の出力を伝送路2の一
端に接続し、伝送路2の他端に伝送路特性インピーダン
スに整合した終端抵抗3と次段集積回路4を接続し信号
伝送を行う方法が、比較的高速のディジタル信号処理回
路で用いられている。Conventionally, as shown in FIG. 2, the output of an integrated circuit 1 is connected to one end of a transmission line 2, and the other end of the transmission line 2 is connected to a terminating resistor 3 that matches the transmission line characteristic impedance and a next-stage integrated circuit 4. Methods of transmitting are used in relatively high speed digital signal processing circuits.
第3図は終端抵抗以降を拡大して表現したもので、図面
符号3は終端抵抗、5はパッケージ、6は集積回路チッ
プ、7はチップ内トランジスタ、図面符号Aはパッケー
ジリード部の長さ、Bはパッケージケース内配線長であ
る。これかられかるように、終端抵抗3が伝送路特性イ
ンピーダンスと整合しても終端抵抗3の位置から実際に
信号の印加されるチップ6内トランジスタ7までの距離
(A+B)がそこを伝播する信号の立上り、立下りおよ
び速度に対し無視できない場合がある。このときトラン
ジスタ7に印加される信号は反射の影響を受は波形歪が
生じる。また、第3図のAおよびBのリード線部分8を
伝送路の特性インピーダンスRに合わせた構造としても
、チップ内トランジスタ7の入力インピーダンスが大き
い場合は、終端抵抗3の後にさらに終端開放に近い状態
の伝送路が接続された状態となり、この場合も波形歪が
起こる。Fig. 3 is an enlarged representation of the terminal resistor and subsequent parts, where 3 is the terminating resistor, 5 is the package, 6 is the integrated circuit chip, 7 is the transistor in the chip, and A is the length of the package lead. B is the wiring length inside the package case. As we will see, even if the terminating resistor 3 matches the transmission path characteristic impedance, the distance (A+B) from the position of the terminating resistor 3 to the transistor 7 in the chip 6 to which the signal is actually applied is the distance of the signal propagating there. There are cases where the rise, fall, and speed cannot be ignored. At this time, the signal applied to the transistor 7 is affected by reflection, causing waveform distortion. Furthermore, even if the lead wire portions 8 of A and B in FIG. The transmission line in the state is connected, and waveform distortion occurs in this case as well.
その解決策として、従来は第4図のように前記リード線
部分A、BとしてパッケージリードA′およびケース内
配線B′を伝送路の特性インピータンスRに合わせ、さ
らに特性インピーダンスRに等しい終端抵抗3′をチッ
プ6内に内蔵する方法が用いられている。As a solution to this problem, as shown in FIG. 3' is built into the chip 6.
しかし、第4図の集積回路チップ6で形成される終端抵
抗3′はきわめて小形のものであり、精度的には±20
〜±30%程度の誤差をもっことは避けられない。した
がって、第3図および第4図のどちらの場合にも伝送路
とのミスマツチにより反射が生じ波形劣化が生じる欠点
を有していた。この反射による劣化を抑えるように内蔵
抵抗のばらつきを±10%に抑えるためには集積回路の
自体の選別も可能であるが、この場合には歩留りの悪化
を招く。However, the terminating resistor 3' formed by the integrated circuit chip 6 in FIG. 4 is extremely small and has an accuracy of ±20
It is unavoidable that there will be an error of about ±30%. Therefore, both the cases of FIG. 3 and FIG. 4 have the disadvantage that mismatch with the transmission line causes reflection and waveform deterioration. Although it is possible to select the integrated circuit itself in order to suppress the variation in the built-in resistance to ±10% so as to suppress the deterioration caused by this reflection, in this case, the yield will deteriorate.
本発明は、上記の問題点を解決するものであり、集積回
路に特性上のばらつきがあっても、反射劣化を極度に減
らした終端抵抗内波形集積回路を提供することを目的と
する。The present invention solves the above-mentioned problems, and aims to provide a waveform integrated circuit within a terminating resistor in which reflection deterioration is extremely reduced even if the integrated circuit has variations in characteristics.
C問題点を解決するための手段〕
本発明は、外部信号を取り込む入力回路が所定の特性イ
ンピーダンスの伝送路に形成され、パンケージ内に内蔵
され、その伝送路と回路内能動素子との接続点に一端が
接続され他端が共通電位点に接続された終端抵抗を備え
た集積回路において、上記パッケージ外の上記伝送路と
共通電位点との間に外付の抵抗が接続され、この外付の
抵抗と上記終端抵抗との並列抵抗値が上記特性インピー
ダンスに近似する値に設定されたことを特徴とする。Means for Solving Problem C] The present invention provides an input circuit that takes in an external signal, which is formed in a transmission line with a predetermined characteristic impedance, is built in a pancase, and has a connection point between the transmission line and an active element in the circuit. In an integrated circuit equipped with a terminating resistor having one end connected to a common potential point and the other end connected to a common potential point, an external resistor is connected between the transmission path outside the package and the common potential point. A parallel resistance value between the resistor and the terminating resistor is set to a value that approximates the characteristic impedance.
パッケージに内蔵の抵抗器はその調整が困難で値のばら
つきが大きくなるが、外付の抵抗器は調整あるいは選定
することができる。この伝送路に生じる反射の大部分は
内蔵の抵抗器で吸収することができる。さらに外付の抵
抗器を接続することにより、一部の抵抗器が伝送路の途
中に接続されることになるが、二つの抵抗器の並列抵抗
値を特性インピーダンスに近似させることにより、外部
から見たこの集積回路の入力回路は特性インピーダンス
の値によく近似していることになり、入力回路の伝送路
の反射を実質的に小さくすることができる。Resistors built into the package are difficult to adjust and have large variations in value, but external resistors can be adjusted or selected. Most of the reflection that occurs on this transmission path can be absorbed by built-in resistors. Furthermore, by connecting an external resistor, some resistors will be connected in the middle of the transmission line, but by approximating the parallel resistance value of the two resistors to the characteristic impedance, it is possible to It can be seen that the input circuit of this integrated circuit closely approximates the value of the characteristic impedance, and the reflection in the transmission path of the input circuit can be substantially reduced.
本発明の実施例装置を図面を用いて説明する。 An embodiment of the present invention will be described with reference to the drawings.
第1図において、駆動側集積回路1の出力段は特性イン
ピーダンスRなる伝送路2の入力に接続され、その中途
のパッケージからの距離がA部分に抵抗値R,なる外付
は抵抗3aが接続される。In Fig. 1, the output stage of the driving integrated circuit 1 is connected to the input of a transmission line 2 with a characteristic impedance R, and an external resistor 3a is connected to a portion A at a distance from the package with a resistance value R. be done.
それに続く長さBはパッケージ5内配線長である。The following length B is the wiring length within the package 5.
上記A、Bで示す部分も特性インピーダンスRの伝送路
2の延長上にある。上記B部の先端はチップ内トランジ
スタを集積回路チップ6a内のトランジスタ7と共通電
位点に接続されるチップ内抵抗3bに接続される。The portions indicated by A and B above are also on the extension of the transmission line 2 having the characteristic impedance R. The tip of the portion B is connected to an on-chip resistor 3b which connects the on-chip transistor to a common potential point with the transistor 7 on the integrated circuit chip 6a.
このチップ内抵抗3bは集積回路チップ内に形成された
抵抗値R2なる終端抵抗である。第1図の場合パッケー
ジ外付は抵抗3aを含め集積回路チ・ノブ6aを見込ん
だ入力インピーダンスはほぼ抵抗値R1とR2の並列接
続と見なせる。ここで集積回路チップ6aに内蔵のチッ
プ内抵抗3bの抵抗値は、前述のように±20〜±30
%程度のばらつきを持つが、外付は抵抗3aの抵抗値の
ばらつきは小さく製造できるので全体としての抵抗値ば
らつきは抵抗3bのばらつきに比べてはるかに低く抑え
るように製造することができる。This in-chip resistor 3b is a terminating resistor with a resistance value R2 formed within the integrated circuit chip. In the case of FIG. 1, the input impedance considering the integrated circuit chip 6a including the resistor 3a external to the package can be considered to be approximately the parallel connection of resistance values R1 and R2. Here, the resistance value of the on-chip resistor 3b built into the integrated circuit chip 6a is ±20 to ±30 as described above.
However, since the externally attached resistor 3a can be manufactured with a small variation in resistance value, the overall resistance value variation can be suppressed to be much lower than that of the resistor 3b.
−例として、50Ωの特性インピーダンスを得る場合に
は、従来の50Ω内藏形式では抵抗値は130%変化す
る可能性があるが、
R+=10QΩ、 Rz =100Ω
として設計した場合には抵抗値R2が+30%、すなわ
ち130Ωとなっても抵抗値R,の精度を高くすると全
体としては最小56.5Ωとすることができ、50Ωか
らの変化は13%に過ぎない。さらに、外付は抵抗3a
の値が調整可能に設計すれば、二つの抵抗の並列抵抗値
を50Ωに近づけることができる。- For example, when obtaining a characteristic impedance of 50Ω, the resistance value may change by 130% in the conventional 50Ω internal circuit type, but if it is designed with R+ = 10QΩ and Rz = 100Ω, the resistance value R2 Even if R becomes +30%, that is, 130Ω, if the precision of the resistance value R is increased, the overall minimum value can be 56.5Ω, and the change from 50Ω is only 13%. Furthermore, the external resistor 3a
If the design allows the value of to be adjusted, the parallel resistance value of the two resistors can be made close to 50Ω.
以上説明したように、本発明によれば、パフケージ内の
伝送路端に接続された抵抗により反射の大部分が吸収さ
れ、さらにこの集積回路の外からこの集積回路の入力回
路を見たインピーダンスは、内蔵の抵抗と外付された抵
抗と合成された抵抗との並列抵抗値となって、伝送路の
特性インピーダンスに近似した値とすることができる。As explained above, according to the present invention, most of the reflection is absorbed by the resistor connected to the end of the transmission line inside the puff cage, and furthermore, the impedance when looking at the input circuit of this integrated circuit from outside the integrated circuit is , the built-in resistor, the external resistor, and the combined resistor have a parallel resistance value, which can be a value that approximates the characteristic impedance of the transmission line.
したがって全体として反射を小さくすることができる。Therefore, reflection can be reduced as a whole.
したがって、集積回路のばらつきが大きくても実用′に
供することができ製造歩留りが向上するとともに、入力
回路の伝送路そのものの特性インピーダンスの調整精度
を従来より緩やかに設定することができることになるか
ら、この面がらも製造工数を小さくすることができる効
果がある。Therefore, even if the integrated circuit has large variations, it can be put to practical use, improving the manufacturing yield, and the adjustment accuracy of the characteristic impedance of the input circuit transmission path itself can be set more gently than before. This aspect also has the effect of reducing the number of manufacturing steps.
第1図は本発明実施例の終端抵抗分割実装回路図。
第2図は従来例の回路構成図。
第3図は他の従来例の回路構成図。
第4図は終端抵抗内蔵形集積回路の従来例回路図。
1・・・集積回路(駆動側)、2・・・伝送路(特性イ
ンピーダンスR)、3.3′・・・H端抵抗、3a・・
・パッケージ外付けけ抵抗(抵抗値Rr ) 、3b・
・・チップ内抵抗(抵抗値R,)、4・・・集積回路(
受は側)、5・・(パッケージ5.6.6a・・・集積
回路チップ、7・・・チップ内トランジスタ、8・・・
伝送リード線部分、A、A’・・・パンケージリード部
、B、B′・・・パッケージ内配線。FIG. 1 is a terminal resistor division mounting circuit diagram of an embodiment of the present invention. FIG. 2 is a circuit configuration diagram of a conventional example. FIG. 3 is a circuit diagram of another conventional example. FIG. 4 is a circuit diagram of a conventional integrated circuit with a built-in termination resistor. 1... Integrated circuit (drive side), 2... Transmission line (characteristic impedance R), 3.3'... H-end resistance, 3a...
・Package external resistor (resistance value Rr), 3b・
...Resistance inside the chip (resistance value R,), 4...Integrated circuit (
(Package 5.6.6a...Integrated circuit chip, 7...Transistor in chip, 8...
Transmission lead wire section, A, A'... Pan cage lead section, B, B'... Wiring inside the package.
Claims (1)
ーダンスの伝送路に形成され、 パッケージ内に内蔵され、その伝送路と回路内能動素子
との接続点に一端が接続され他端が共通電位点に接続さ
れた終端抵抗を備えた 集積回路において、 上記パッケージ外の上記伝送路と共通電位点との間に外
付の抵抗が接続され、 この外付の抵抗と上記終端抵抗との並列抵抗値が上記特
性インピーダンスに近似する値に設定された ことを特徴とする集積回路。(1) An input circuit that takes in an external signal is formed on a transmission path with a predetermined characteristic impedance, is built into a package, and one end is connected to the connection point between the transmission path and the active element in the circuit, and the other end is connected to a common potential point. In an integrated circuit equipped with a terminating resistor connected to an external resistor, an external resistor is connected between the transmission line outside the package and a common potential point, and the parallel resistance value of this external resistor and the terminating resistor is An integrated circuit characterized in that the characteristic impedance is set to a value approximating the characteristic impedance described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22413885A JPS6282807A (en) | 1985-10-08 | 1985-10-08 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22413885A JPS6282807A (en) | 1985-10-08 | 1985-10-08 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6282807A true JPS6282807A (en) | 1987-04-16 |
Family
ID=16809141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22413885A Pending JPS6282807A (en) | 1985-10-08 | 1985-10-08 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6282807A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63256001A (en) * | 1987-04-14 | 1988-10-24 | Toshiba Corp | Integrated circuit device |
| JP5752862B1 (en) * | 2014-06-18 | 2015-07-22 | ゼンテルジャパン株式会社 | Semiconductor circuit device and semiconductor memory system |
-
1985
- 1985-10-08 JP JP22413885A patent/JPS6282807A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63256001A (en) * | 1987-04-14 | 1988-10-24 | Toshiba Corp | Integrated circuit device |
| JP5752862B1 (en) * | 2014-06-18 | 2015-07-22 | ゼンテルジャパン株式会社 | Semiconductor circuit device and semiconductor memory system |
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