JPH01143996A - Alarm clock - Google Patents

Abstract

PURPOSE:To obviate generation of an excessive or deficient sound volume by setting adequate criteria to respective persons and controlling the sound volume of an alarm now under working in accordance with the criteria. CONSTITUTION:A pulse generating circuit 28 generates a pulse signal in response with the alarm stop operation of an alarm stop switch 26. An alarm time counting circuit 30 counts the output time of an alarm operation signal and outputs an alarm time signal. An accumulated time generating circuit 36 outputs an accumulated time signal in response with the pulse signal and an operation time counting circuit 42 outputs an operation times signal by counting the pulse signals. A divisor counting circuit 44 and dividend counting circuit 50 preset the accumulated time signal and operation times signal in response with the pulse signals. A clock generating circuit 52 and an average value counting circuit 60 respectively stop the output of the clock signal and output average value signal in response with the carry signals outputted from the circuits 44 and 50. A comparator circuit 68 compares the alarm time signal and the average value signal and outputs the output signal to an alarm circuit 70.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to an alarm clock that controls the volume of an alarm based on the alarm sounding time, and in particular, the present invention relates to an alarm clock that controls the volume of an alarm based on the alarm sounding time, and in particular, a watch that controls the volume of an alarm based on the average value of past alarm sounding times. This relates to a device that increases the alarm volume when the alarm sounding time becomes longer than this.

(b) Prior art As a conventional alarm clock of this type, the
There is one disclosed in Japanese Patent No. 674.

In this alarm watch, when the alarm continues for a certain period of time, it is determined that the current alarm volume will not wake the user, and the alarm volume is increased at the next alarm notification.

(c) Problems to be solved by the invention In general, there is not necessarily a correlation between the current situation and the next time the alarm is reported. It does not necessarily mean that they are the same.

Therefore, in the conventional example, the volume may be too high even though you woke up early because the previous alarm sounded for a long time, or the volume may be insufficient because the previous alarm sounded for a short time even though you do not wake up easily. This was not efficient, as the alarm volume could be too high or too low.

The purpose of the present invention is to provide an efficient alarm clock that does not have too much or too little volume by setting appropriate judgment criteria for each person and controlling the volume of the alarm that is currently being worked based on this criteria. It is to be.

(d) Means for Solving the Problems In order to solve the above problems and achieve the purpose, the alarm clock of the present invention has a clock section, an alarm circuit, and a ring stop switch. A pulse generation circuit that outputs a pulse signal in response to the operation of the stop switch, a ringing time counting circuit that outputs a ringing time signal indicating the alarm operation time, and a ringing time signal that is successively accumulated in response to the pulse signal. A cumulative time generating circuit that outputs a time signal, an operation counting circuit that counts pulse signals and outputs an operation number signal, a dividend counting circuit that presets the cumulative time signal in response to the pulse signal, and a dividend counting circuit that presets the cumulative time signal in response to the pulse signal. a divisor count circuit that presets the operation number signal;
a clock generation circuit that supplies a clock signal to both count circuits in response to the pulse signal and stops supplying the clock signal in response to the output of a carry signal from the dividend count circuit;

an average value counting circuit that counts carry signals output from the divisor count circuit and outputs an average value signal; a comparison circuit that compares the ringing time signal and the average value signal and outputs a comparison signal; The present invention is characterized in that it is provided with a notification circuit for notifying an alarm sound of a corresponding volume.

(e) Function In the alarm clock of the present invention, the ringing time of the alarm is counted each time an alarm is notified by the ringing time counting circuit, and the counted value is sequentially added and accumulated by the cumulative time generating circuit.

Further, the operation counting circuit counts the number of times the ring stop switch is operated as the number of times the alarm is operated.

The alarm ringing time accumulated by the cumulative time generating circuit and the number of alarm operations counted by the operation counting circuit are preset in the dividend counting circuit and the divisor counting circuit, respectively.

For example, if the accumulated alarm sounding time is 40 seconds and the number of alarm operations at this time is 4, the dividend count circuit and divisor count circuit will output "40" and "4", respectively.
preset to .

Therefore, the dividend count circuit outputs a carry signal when it counts "40", and the divisor count circuit outputs a carry signal when it counts "40".
When ``1-'' is input, a carry signal is output.

Here, a clock signal is applied from the clock generation circuit to this rain counting circuit, and both counting circuits start counting at the same timing.

As a result, the divisor counting circuit counts "4" ten times before the dividend counting circuit counts "40". That is, the average value can be determined by counting how many times the divisor count circuit outputs a carry signal before the dividend count circuit outputs a carry signal.

The carry signal of this divisor counting circuit is counted by the average value counting circuit.

The average value signal output from this average value counting circuit is applied to a comparison circuit, where it is compared with the alarm sounding time in operation. As a result, when the alarm sounding time becomes longer than the average value, the comparison circuit outputs a comparison signal, and in response to this signal, the notification circuit increases the volume of the alarm sound.

(f) Examples The present invention will be described in detail below based on the drawings.

The drawing is a diagram showing a circuit configuration of an alarm watch according to an embodiment of the present invention.

Reference numeral 2 designates a clock section, which includes an oscillation circuit 4, a frequency dividing circuit 6 that divides the frequency of its output signal, a waveform shaping circuit 8 that shapes the waveform of its output signal, and a drive circuit 10 that converts its output signal into a drive signal. a motor 12 driven by a drive signal; a wheel train 14 driven by the motor 12;
4, and a guide mechanism 18 that detects the set alarm time from the movement of the train.

20 is an alarm circuit, and 26 is a ringing stop switch.

This alarm circuit 20 includes a one-shot multivibrator (hereinafter referred to as "O8") 22 which inputs the signal output from the reference mechanism 18 when the alarm time comes, and the output signal and the operation signal from the ring stop switch 26. A flip-flop (which inputs to the clock power φ and reset power R, respectively, and whose data input is connected to the power supply)
(hereinafter abbreviated as rFFJ) 24.

28 is a pulse generating circuit which outputs a single pulse when an operation signal from the anti-ringing switch 26 is input.

30 is a ringing time counting circuit, which receives the alarm operation signal from the output Q of the FF 24 in the alarm circuit 20 and the frequency dividing circuit 6.
AND gate 32 which inputs the clock signal φ□ from
and input its output signal to clock input φ and ○S2
and a ringing time counter 34 which inputs the pulse from 2 to the reset human power R.

Reference numeral 36 denotes an accumulation time generating circuit, which is composed of an adding circuit 38 and a register 40. This adder circuit 38 receives the ringing time signal output from the ringing time counter 34 and the signal from the register 40, adds them together, and outputs a cumulative time signal.

Further, the register 40 inputs the single pulse from the pulse generating circuit 28 to the preset input PE, and further inputs the cumulative time signal. This register 40 stores the cumulative time signal when a single pulse is input to the preset input PE.

Reference numeral 42 denotes an operation number circuit consisting of an operation number counter which inputs a single pulse from the pulse generating circuit 28 to the clock input φ and outputs an operation number signal.

44 is a dividend counting circuit, and a pulse generating circuit 28
Delay circuit 4 that inputs a single pulse from and delays it for a certain period of time.
6 and a dividend counter 48.

The dividend counter 48 inputs the signal from the delay circuit 46 and the cumulative time signal from the adder circuit 38, and when the signal from the delay circuit 46 is input to the preset manual PE, the cumulative time signal is preset.

Further, this dividend counter 48 inputs a clock signal from a clock generation circuit, which will be described later, to a clock input φ.
A carry signal from output C is applied to the clock generation circuit.

5o is a divisor counting circuit consisting of a divisor counter.

This divisor count circuit 50 inputs the signal from the delay circuit 46 and the operation number signal from the operation number counter 42,
When the signal from the delay circuit 46 is input to the preset input PE, the operation number signal is preset.

Further, this divisor count circuit 50 inputs a clock signal from a clock generation circuit, which will be described later, to a clock input φ,
A carry signal is output from output C.

52 is a clock generation circuit, and a delay circuit 54 receives a single pulse from the pulse generation circuit 28 and delays it for a longer time than the delay circuit 46.

The FF inputs the output signal and the carry signal from the dividend counter 48 to the set manual power S and the reset manual power R, respectively.
56, and an AND gate 58 which inputs the signal from its output Q and the clock signal φ2 from the frequency divider circuit 6 and applies its output signal to the dividend count circuit 44 and the divisor count circuit 50.

60 is an average value counting circuit, which includes an average value counter 62 that inputs the carry signal from the divisor count circuit 50 and the signal from the delay circuit 46 to the clock manual power φ and the reset manual power R, respectively, and outputs an average value signal; and a battery. An initial reset circuit 64 that outputs a signal when the power is turned on, etc., and an average value counter 6 that outputs a signal indicating a predetermined time when the output signal is input.
2, and an encoder 66 that applies the voltage to the signal.

68 is a comparison circuit which inputs the ringing time signal from the ringing time counting circuit 30 and the average value signal from the average value counting circuit 60, and outputs a comparison signal.

70 is a notification circuit, which includes a notification signal generation circuit 72 which inputs an alarm operation signal from the alarm circuit 20 and outputs a notification signal, and a notification signal generation circuit 72 which inputs the notification signal and a comparison signal from the comparison circuit 68 and outputs a drive signal. The drive circuit 74 includes a drive circuit 74, and a speaker 76 that emits an alarm sound when a drive signal is input.

Next, the operation of the alarm clock having the above configuration will be explained.

First, when the alarm time comes and a signal is output from the reference mechanism 18, the 0 signal in the alarm circuit 20 to which this signal is input is output.
A pulse is output from 822.

At this time, the ringing time counter 34, divisor counter 48, and divisor count circuit 50, which input this pulse to the reset human power R, are reset.

Also, the FF24 inputs this pulse to the clock input φ.
sets the alarm operation signal from its output Q to H level in synchronization with the rising edge of this pulse.

When this alarm operation signal becomes H level, the notification circuit 7
In response to this, the notification signal generation circuit 72 in 0 outputs a notification signal, and in response to this notification signal, the drive circuit 74 applies a drive signal to the speaker 76 to generate an alarm sound.

If the alarm notification at this time is the first alarm notification after battery insertion, the average value has not been calculated yet, so
The average value counter 62 in the average value counting circuit 60 applies a predetermined value output from the preset encoder 66 when the initial reset circuit 64 outputs the signal to the comparison circuit 68 as an average value signal. Note that the values preset in the average value counter 62 are 5 seconds and 10 seconds.
It indicates time such as seconds.

On the other hand, the ringing time counter 34 in the ringing time counting circuit 30, which applies the ringing time signal to the comparison circuit 68, clocks the clock signal φ1 generated at the output of the AND gate 32, which is open only during alarm operation. Enter the input φ to count the alarm sounding time.

The comparison circuit 68, which receives the ringing time signal indicating the alarm ringing time and the average value signal indicating a predetermined time, compares these signals and determines if the alarm ringing time is longer than the predetermined time. , for example, switches the output comparison signal from L level to H level.

In response to such a change in the comparison signal, the drive circuit 74
The volume of the output drive signal is increased to increase the alarm sound.

When the ring stop switch 26 is operated here, an H level operation signal is applied to the human reset force R of the FF 24 in the alarm circuit 20, thereby resetting the FF 24. Therefore, the alarm operation signal from the output Q of the FF 24 becomes L level, and the alarm notification is stopped.

Further, the pulse generating circuit 28 outputs a single pulse in response to the operation of the ring stop switch 26.

This single pulse is generated by the register 4 in the cumulative time generating circuit 36.
A preset human power PE of 0 is applied.

This register 40 presets the cumulative time signal output by the adder circuit 38 in response to this single pulse.

This adder circuit 38 outputs the ringing time signal from the ringing time counter 34 as it is since nothing is stored in the register 40 at the time of the first alarm notification after battery insertion, and registers it at the time of the second and subsequent alarm notifications. 40
The sum of the stored value and the ringing time signal is output.

Therefore, the register 40 stores the added value of the ringing time signal up to the previous time, and the adding circuit 38 further adds the ringing time signal to this added value every time an alarm is notified, and outputs it as a cumulative time signal. It turns out.

At this time, the single pulse from the pulse generating circuit 28 is also applied to the clock input of the operation counting circuit 42 to increment its count value by one.

Also, after that, the delay circuit 4 in the dividend count circuit 44
The single pulse delayed at step 6 is applied to each preset PE of the dividend counter 48 and the divisor counting circuit 50, and the dividend counter 48 and the divisor counting circuit 50 respond to the single pulse and generate a cumulative time signal and a cumulative time signal, respectively. The count value is preset to the value indicated by the operation number signal.

Furthermore, after that, the delay circuit 54 in the clock generation circuit 52
The single pulse delayed at is applied to the set input S of the FF 56 to set it. When this FF 56 is set and the signal from its output Q goes to H level, the AND gate 58 becomes open and the clock signal φ is sent to its output.
2 occurs.

This clock signal φ2 is applied to each clock signal φ of the dividend counter 48 and the divisor count circuit 50. As a result, the dividend counter 48 and the divisor count circuit 5o start counting at the same timing, and when each counts up to a preset value, a pulse is output from the output C as a carry signal. As mentioned above, the cumulative time signal indicating, for example, 40 seconds is preset in the dividend counter 48.

Further, if the operation number signal indicating 4 times is preset in the divisor count circuit 50, the divisor count circuit 50 will output the carry signal 10 times before the dividend counter 48 outputs the carry signal.

When the carry signal is output from the dividend counter 48 in this manner, the FF 56 in the clock generation circuit 52 is reset, and the signal from its output Q is set to L level. Therefore, the AND gate 58 is closed and stops outputting the clock signal.

On the other hand, the carry signal output by the divisor count circuit 50 is
A single pulse from the delay circuit 46 is applied to the clock input φ of the average value counter 62, which has already been reset. This average value counter 62 counts the carry signal from the divisor counting circuit 50 and outputs the counted value as an average value signal.

This average value signal is applied to the comparator circuit 68, as described above, where it is compared with the ringing time signal.

In this way, each time the ring stop switch 26 is operated, the average ringing time is calculated from the number of alarm activations and the accumulated ringing time corresponding to the number of alarm activations, and the next time the alarm is activated, the alarm is set based on this average ringing time. If the ringing time is longer than this, the volume of the alarm sound will be increased.

In this embodiment, the output timing of the single pulse output from the pulse generation circuit 28 is shifted by the delay circuits 46 and 54 and applied to each circuit, but the output timing from the pulse generation circuit 28 is By outputting a plurality of pulses with different values, the pulses may be directly applied to each circuit without using the delay circuits 46 and 54.

(g) Effects of the Invention According to the present invention, the average value of the user's alarm ringing time several times is used as a standard, and appropriate judgment criteria are set for each person, and control is applied to the alarm that is currently in operation. is carried out, so the alarm volume is not too high or too low, making it efficient.

[Brief explanation of the drawing]

The drawing is a diagram showing a circuit configuration of an alarm watch according to an embodiment of the present invention. 2...Clock part, 20...Alarm circuit 2
6...Sound stop switch. 28...Pulse generation circuit, 30...Ring time counting circuit, 36...Cumulative time generation circuit. 42... Operation counting circuit, 44... Dividend counting circuit, 50... Divisor counting circuit. 52... Clock generation circuit, 60... Average value counting circuit, 68... Comparison circuit 70.
...Notification circuit.

Claims (1)

[Scope of Claims] A clock unit that outputs a trigger signal at a set time, an alarm circuit that outputs an alarm operation signal in response to the output of the trigger signal, and a ring stop switch that stops outputting the alarm operation signal. , a pulse generation circuit that outputs a pulse signal in response to a ring stop operation of the ring stop switch; and a ring time counting circuit that counts the output time of the alarm operation signal and outputs a ring time signal. , an accumulation time generation circuit that sequentially accumulates the ringing time signal in response to the output of the pulse signal and outputs a cumulative time signal; and an operation counting circuit that counts the output of the pulse signal and outputs an operation number signal. , a dividend count circuit that presets the cumulative time signal in response to the output of the pulse signal, a divisor count circuit that presets the operation number signal in response to the output of the pulse signal, and a divisor count circuit that responds to the output of the pulse signal. a clock generating circuit that supplies a clock signal to both of the count circuits and stops outputting the clock signal in response to the output of a carry signal from the dividend count circuit; and a carry output from the divisor count circuit. an average value counting circuit that counts signals and outputs an average value signal; a comparison circuit that compares the ringing time signal and the average value signal and outputs a comparison signal; A clock with an alarm, comprising: a notification circuit that notifies an alarm sound at a volume corresponding to the output of a comparison signal;