JPH01144665A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device in which a plurality of elements are integrated into one chip.

(Prior art) Conventionally, a method for manufacturing a semiconductor device in which a high-power power transistor and a control circuit are integrated into a single chip is described in the Institute of Electrical Engineers of Japan study group material (
EDD-87-61). That is, Fig. 5 (
In the manufacturing steps shown in a) to (e), after forming SiO2 films 3 and 4 on the silicon substrates 1 and 2 as shown in FIG. Directly join the vertical power MO3+ as shown in the same figure (C).
~Remove part of the 3i section and 5i02 section to form a transistor. After that, epitaxial growth is performed on the substrate (wafer) (after the epitaxial layer 5 is formed) as shown in FIG. 4(d), and then etching is performed to planarize the surface (FIG. 2(e)). After that, a region P1 separated by the 5i02 films 3 and 4 and the separation layer 6 is formed, and this region P1
In addition, an N-channel transistor, a P-channel transistor, etc. are formed in the region P2 of the epitaxial layer 5, and a power MOS transistor is formed in the region P2 of the epitaxial layer 5.

(Problems to be Solved by the Invention) However, in the conventional semiconductor device manufacturing method described above, the region P2 for forming the vertical element (power MOS transistor) is formed by the silicon substrate 1.2, the SiO2 film 3
, 4 is removed, an epitaxial layer 5 is formed, and a polishing step is required to form the device. This process is complicated, yields are low, and losses increase from 1 to 10%.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and provide a method of manufacturing an isolated semiconductor device that is easy to manufacture and inexpensive.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a step of forming an insulating film in a predetermined region of the first semiconductor substrate or its main surface; a step of smoothing the surface; a step of bonding the main surface of the first semiconductor substrate to the smooth main surface of the second semiconductor substrate; The gist thereof is a method for manufacturing a semiconductor device, comprising the steps of forming a separation layer that extends to a film to separate electrically isolated regions, and forming an element in each region separated by the separation layer. It is something to do.

(First Embodiment) The first embodiment embodying the present invention will be described below as shown in Fig. 1(a).
This will be explained according to (Q).

As shown in FIG. 1(a), for example, P (phosphorus), A
An N+ layer 12 is formed by diffusion of S (arsenic), etc., and the N
A thermal oxide film (SiO2) 13 as an insulating film on the + layer 12
is formed to a thickness of 0.5 to 1 μm in, for example, 100 O'C steam.

Next, as shown in FIG. 1(b), after removing unnecessary parts of the thermal oxide film 13, so-called epitaxial growth is performed at 1000 to 1200'C while flowing P and AS impurities. An epitaxial layer 14 having a thickness of 5 μm is grown at a high temperature of N. At this time, an N+ polysilicon layer 15 is formed on the thermal oxide film 13. Note that the N+ high concentration portion may be formed later by diffusion or ion implantation without introducing impurities during epitaxial growth. This first
The substrate not shown in FIG. 2B becomes a first semiconductor substrate in which an insulating film is formed in a predetermined region within the substrate.

Next, as shown in FIG. 1C, the main surface of the silicon substrate 11 is polished to a so-called mirror surface to form an epitaxial layer 14.
and polysilicon layer 15 to form smooth surfaces so that they have the same height.

Subsequently, a single crystal N+ silicon substrate 1 as a second semiconductor substrate containing P, As, Sb, etc. shown in FIG.
6 is prepared, and the main surface of this substrate 16 is mirror polished. Then, the main surfaces of these two substrates IL16 are
For example, use RCA cleaning to make the surface clean and free of dust and other oils. Then, as shown in FIG. 1(e), the mirror surfaces (main surfaces) of both substrates 1.1.16 are glued together, and the substrates 11.16 are inserted into a furnace at 800 to 1200'C. The main surfaces are strongly joined by so-called direct joining. In FIG. 1(e), the N+ silicon substrate 16 is located on the lower side, and the N- silicon substrate 11 is located on the upper side.

At this time, for example, when forming a vertical power MOS transistor in the future, the junction between the epitaxial layer 14 and the N+ silicon substrate 16 is made of single crystal, so the resistance component of the junction becomes extremely small, resulting in improved performance. be able to.

Next, as shown in FIG.
1 to a predetermined thickness if necessary, trench isolation is formed on the N-silicon substrate 11, and a region P3.1 is electrically isolated using a thermal oxide film 13.
A separation layer is formed to separate P4. This trench isolation is performed by, for example, using a SiO2 film or the like as a mask (not shown) and etching the N-silicon substrate 11 partially down to the thermal oxide film 13 using reactive ion etching to form a trench that reaches the thermal oxide film 13. This is done by forming an oxide film 17 as an isolation layer on the sidewalls of the trench by thermal oxidation or CVD, and then burying polysilicon 18 as an isolation layer in this trench portion and removing the excess portion by polishing.

Subsequently, each region P3 separated by a separation layer (oxide film 17, polysilicon 18) An element is formed on P4. That is,
The vertical power MO8l to transistor 19 shown in FIG. 1 (CI) are formed by a normal method in the part where 3i of both substrates 11.16 are joined (region P3), and the region of the N+ silicon substrate 16 is Use as a drain part. on the other hand,
Thermal oxide film 13 and oxide film 17. In this embodiment, a region P4 (FIG. 1(f)) separated by polysilicon 18 is formed by ion implantation and drive-in of NWel+ to form a region 20 of an arbitrary concentration, and a P-channel MOS transistor 21 is formed. do. In FIG. 1 (Ω)+, 22 is a P region, 23 is a P region, and 24 is an N+ region.

In this case, NWel+ is formed, but pWel+ may be formed to form an N-channel MOS transistor or a bipolar transistor, and furthermore, a logic circuit may be formed by combining them.

Further, in FIG. 1(Q), the thermal oxide film 13 and the oxide film 17. Although only one region P4 isolated by polysilicon 18 is shown, it goes without saying that a plurality of isolation regions may be formed.

Subsequently, polysilicon layers 1 to 1, source and drain impurity regions, wiring layers, etc. (not shown) are formed to form a composite IC.

In this way, in the present embodiment, the process is complicated, the yield is low, and the cost is high in the conventional method of manufacturing a semiconductor device.
A process such as etching for removing a portion of the O2 films 3 and 4 is not necessary, and a semiconductor device in which elements can be separated can be manufactured with a simple process. Therefore, a semiconductor device that is easy to manufacture and inexpensive can be obtained.

(Second example) Next, a second embodiment of the present invention is shown in FIG. 2(a).

This will be explained using (b).

In the first embodiment, the thermal oxide film 13 and the thermal oxide film 13 are
An epitaxial layer 14 is formed on the N+ layer 12 which is not covered with
Then, as shown in FIG. 2(a), an amorphous silicon layer 25 is formed by plasma deposition. after that,
So-called solid phase epitaxial growth (500~1100°
C heat treatment), and at least single crystal (N+1i12
) is grown by solid-phase epitaxial growth to convert most of it into single crystal silicon, and a thermal oxide film 13 is formed on the amorphous layer.
The top layer is changed to polysilicon.

Then, the ion-implanted region is made into an N+ high) layer by diffusion or ion implantation of P, AS, etc. In this case, when forming the amorphous silicon layer 25, impurities may be simultaneously introduced to increase the concentration of N+.

Subsequently, as shown in FIG. 2(b), mirror polishing is performed to smooth the surface.゛The subsequent steps proceed in the same manner as the steps described above. In this embodiment, the amorphous silicon layer 25 is formed by plasma deposition, but after forming the polysilicon layer, it may be made amorphous by implanting ions of Si, As, P, etc., and subsequently grown by in-phase epitaxial growth.

(Third example) Next, a third embodiment of the invention will be described.

In the first embodiment, epitaxial growth was performed on the thermal oxide film 13 and the N+ layer 12 of the N- silicon substrate 11, but polysilicon was formed by LPCVD on the thermal oxide film 13 and the N+ layer 12, and then As etc. inject. continue,
Polishing is performed for smoothing, and subsequent steps are performed in the same manner as in the previous embodiment.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIGS. 3(a) to 3(g).

As shown in FIG. 3(a), an N+ layer 27 containing P, AS, Sb, etc. is formed on a silicon substrate 26 as a first semiconductor substrate of N type (100) of, for example, 5 to 10 Ω·cm. A pad silicon oxide film 28 of 200 to 1000 Å is formed on the N+ layer 27 by oxidation. Continuing, 500
~200OA silicon nitride film (S!3N4) 29 L
S is deposited by the PCVD method, removed by normal photolithography and etching, and formed into an insulating film of 1 to 2 μm as shown in FIG. 3(b) by the so-called LOCOS oxidation method.
i 02 LOCO3 region 30 is formed.

Next, as shown in FIG. 3(C), the main surface of the substrate 26 is smoothed by mirror polishing.

On the other hand, a ('100) silicon substrate 31 containing high concentration P, AS, etc. as a second semiconductor substrate shown in FIG.
Prepare and mirror-polish the surface in the same way to make it smooth. Then, the main surfaces of these two substrates 26° 31 are
Make the surface clean and free of dust and other oils by CA cleaning etc.

Then, as shown in FIG. 3(e), both substrates 26.
The mirror surfaces of No. 31 are bonded together and inserted into a furnace at 800 to 1200'C to firmly bond the main surfaces of both substrates by so-called direct bonding.

Thereafter, in the same manner as in the first embodiment described above, the process shown in FIG. 3(f) is performed.
Formation of wrench isolation shown in FIG. 1 to FIG. 3(g) and each element shown in FIG. 3(g) are performed.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described using FIGS. 4(a) to 4(C).

In the fourth embodiment, the main surface of the N-silicon substrate 26 and the silicon substrate 31 are smoothed by mirror polishing.
Although the entire area of S i 02 L' was directly bonded, a recess 32 was formed on the surface of S i 02 as shown in FIG. 4(a).
The OCO8 region 30 and the silicon substrate 31 are not directly bonded to each other. That is, the silicon substrate 31 and the N-silicon substrate 2 as the second semiconductor substrate shown in FIG. 4(b)
6 is joined, it becomes 5i02L as shown in Fig. 4(C).
A space 33 is created between the OCO8 region 30 and the surface of the silicon substrate 31.

This method can be achieved by simply etching away the Si 02 LOCOS region 30 using Si 02 etching solution after LOCO3. Alternatively, after smoothing the surface in the fourth example by mirror polishing, Si
A space 33 can be formed by slightly etching away the 02 LOCO3 region 30.

In this composite IC, as mentioned above, the vertical power M
It is sufficient that the drain of O8 is directly connected to 5i-8i, and there is no need for silicon substrate 31 and 5i02 Locos region 30 to be connected to each other. Furthermore, by forming a space 33 here, this S! 02 LOCO3 area 30
The upper insulator-separated region is S! 02 LOCOS
The region 30 and the space 33 are electrically and thermally insulated, resulting in a more preferable state. In the wafer process, this space 33 is contained within silicon, so there is no problem.

Effects of the Invention As described in detail above, the present invention exhibits the excellent effect of providing a method of manufacturing an isolated semiconductor device with a simple and inexpensive manufacturing process.

[Brief explanation of the drawing]

FIGS. 1(a) to (Ω) are diagrams for explaining the manufacturing process of the semiconductor device of the first embodiment of the present invention, and FIGS. 2(a) and (b)
) are diagrams for explaining the manufacturing process of the semiconductor device of the second embodiment, FIGS. 3(a) to (q) are diagrams for explaining the manufacturing process of the semiconductor device of the fourth embodiment, and FIG. (a) ~ (C)
5A to 5E are diagrams for explaining the manufacturing process of the semiconductor device of the fifth embodiment, and FIGS. 5A to 5E are diagrams for explaining the manufacturing process of the conventional semiconductor device. 11 is an N-silicon substrate, 13 is a thermal oxide film as an insulating film, 16 is an N-silicon substrate as a second semiconductor substrate, 17 is an oxide film as an isolation layer, 18 is polysilicon as an isolation layer, 19 is the power MO8 transistor, 21
2 is a P-channel MOS transistor, 26 is an N-silicon substrate as a first semiconductor substrate, 30 is a SiO2 LOCO8 region as an insulating film, 31 is a silicon substrate as a second semiconductor substrate, 32 is a recess, and 33 is a space. Patent applicant Nippondenso Co., Ltd. Agent
Patent Attorney On 1) Hironobu No. (a) (b) (d) (e) (su)

Claims (1)

[Claims] 1. A step of forming an insulating film in a first semiconductor substrate or a predetermined region of its main surface; a step of smoothing the main surface of the first semiconductor substrate; and a step of smoothing the main surface of the first semiconductor substrate. A step of bonding the main surface of the semiconductor substrate and the smooth main surface of the second semiconductor substrate, and forming a separation layer on the first semiconductor substrate or the second semiconductor substrate up to the insulating film, and electrically A method for manufacturing a semiconductor device, comprising the steps of dividing regions to be separated, and forming elements in each region separated by the separation layer. 2. The step of forming an insulating film within the first semiconductor substrate or in a predetermined region of its main surface includes forming a thermal oxide film as an insulating film in a predetermined region of the main surface of the single crystal silicon substrate, and removing the thermal oxide film. A polysilicon layer is formed on the thermal oxide film by epitaxial growth on the main surface of a single-crystal silicon substrate, and an epitaxial layer is formed on the single-crystal silicon substrate, and the main surface of the first semiconductor substrate is smoothed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of polishing smoothes the epitaxially grown polysilicon layer and the epitaxial layer by polishing. 3. The step of forming an insulating film within the first semiconductor substrate or in a predetermined region of its main surface is to form a thermal oxide film as an insulating film in a predetermined region of the main surface of the single crystal silicon substrate, and then remove the thermal oxide film. An amorphous silicon layer is formed on the main surface of the single crystal silicon substrate by plasma deposition, and then the amorphous silicon layer on the thermal oxide film is made into polysilicon by solid phase epitaxial growth, and the amorphous silicon layer on the single crystal silicon substrate is According to claim 1, the first semiconductor substrate is made into a single crystal, and the step of smoothing the main surface of the first semiconductor substrate is by polishing the polysiliconized and single crystal silicon layer. A method of manufacturing the semiconductor device described above. 4. The step of forming an insulating film in a predetermined region of the first semiconductor substrate or its main surface is to form an SiO_2 LOCOS region as an insulating film in a predetermined region of the main surface of the single crystal silicon substrate by LOCOS oxidation method. Yes, first
The step of smoothing the main surface of the semiconductor substrate is the SIO_
2. The method of manufacturing a semiconductor device according to claim 1, wherein the main surface including the 2LOCOS region is smoothed by polishing. 5. The step of forming an insulating film in a predetermined region of the first semiconductor substrate or its main surface is to form an SiO_2 LOCOS region as an insulating film in a predetermined region of the main surface of the single crystal silicon substrate by LOCOS oxidation method. Yes, first
In the step of smoothing the main surface of the semiconductor substrate, a recess is formed in the SiO_2LOCOS region with respect to the main surface of the single crystal silicon substrate, and the main surface of the first semiconductor substrate and the smooth second The semiconductor substrate according to claim 1, wherein the step of bonding the main surfaces of the second semiconductor substrate is such that a space is formed between the recess and the main surface of the second semiconductor substrate by bonding both substrates. Method of manufacturing the device.