JPH08330554A - Semiconductor substrate and its manufacture - Google Patents

Abstract

PURPOSE: To obtain an optimum semiconductor substrate as a substrate for monolithically integrating a vertical power element and a control circuit element. CONSTITUTION: A cavity 3 is formed between an insulating layer 2 in a region 8 for forming a control circuit element and a single crystal silicon substrate 4, and bonding surfaces 1a, 4a of the single crystal silicon substrates 1, 4 are bonded to each other. Since the sticking of a region in which a vertical power element is formed is performed by mutually sticking flat single crystal silicon surfaces, voids (unbonding parts) are not generated in a bonding surface of the region in which the vertical power element is formed. Thereby, a semiconductor device having a perfect junction wherein electric conduction in the direction perpendicular to the bonding interface is present can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate structure and manufacturing method, and more particularly to an SOI substrate structure and manufacturing method useful for power ICs.

[0002]

2. Description of the Related Art A substrate bonding method is a method for manufacturing a multilayer film structure substrate such as an SOI substrate, which has recently been improved in its bondability and expanded in its applications. In particular, various SOI substrates can be manufactured by applying this method. SO
The I substrate has been put to practical use as a high voltage device for power control and is expected to operate at a high speed in a low voltage operation. Therefore, the I substrate is attracting attention as a substrate material for a next-generation CMOS device. Currently, in the field of power devices, in order to make devices highly integrated and highly reliable, development of intelligent power ICs in which a power device with high withstand voltage and large current and a control circuit device with low withstand voltage are formed on the same chip are under development. It is being actively conducted.

In this intelligent power IC, a vertical power device in which a source and a gate are formed on the same surface on which a control circuit is formed and a drain is formed on the opposite surface in order to improve the driving current amount of the power device. Will be needed. Intelligent power with such a structure I
A partial SOI substrate is used in which the control circuit can be formed on the SOI layer in C. This type of partial SOI substrate is known from JP-A-4-29353 and JP-A-6-156451.

FIG. 8 is a sectional view showing the method of manufacturing an SOI substrate disclosed in Japanese Patent Laid-Open No. 4-29353 (hereinafter referred to as a first conventional example) in the order of steps.

First, as shown in FIG. 8A, a photoresist having a predetermined pattern is formed by photolithography on one main surface of the n ⁺ type single crystal silicon substrate 4, and this is used as a mask to perform an ion etching method. To form a shallow step, and the insulating film 2 of SiO ₂ is formed by thermal oxidation or low temperature CVD.

Next, as shown in FIG. 8 (b), the insulating film 2 which is the convex portion of the step portion is removed by grinding, polishing or etching to insulate the exposed surface of the n ⁺ type single crystal silicon substrate 4 from the exposed surface. The surface of the film 2 is flattened.

The flat surface obtained as described above and the main surface of the main surface 1 of another n ⁺ type single crystal silicon substrate 1 are bonded to each other, heat-treated, and a single strongly bonded composite sheet is formed. A substrate is obtained (FIG. 8 (c)).

Next, the n ^-- type single crystal silicon substrate 1 is ground and polished to the YY plane of FIG.
To a desired thickness and the surface thereof is flattened to form a single crystal silicon active layer 5. After that, the insulating film 10 is formed on the flattened surface, and the insulating film 10 is formed into a required pattern by a photo-etching method. Using this as a mask, alkali etching is performed to form isolation trenches for element isolation, and The type power element formation region and the control circuit element formation region are separated, and the single crystal silicon active layer 5 in the control circuit element formation region is divided into single crystal silicon islands 9.

Next, n ^{− is formed} by thermal oxidation or low temperature CVD.
An insulating film 10 made of SiO ₂ or the like is formed on the surface of the mold single crystal silicon substrate 1, and then a polycrystalline silicon layer 11 is formed by a CVD method. Then, the polycrystalline silicon layer 11 and the insulating film 10 on the surface of the substrate are removed by grinding / polishing or etching, while the isolation groove is filled with the insulating film 10 and the polycrystalline silicon layer 11 to insulate the element formation regions from each other. An SOI substrate is obtained (FIG. 8 (d)).

Next, referring to FIG. 9, Japanese Unexamined Patent Publication No. 6-15645
Another conventional technique (hereinafter referred to as a second conventional example) related to the partial SOI substrate disclosed in Japanese Patent No. 1 will be described.

First, as shown in FIG. 9A, a silicon oxide film having a uniform thickness is formed on one main surface of the n ^-- type single crystal silicon substrate 1 by a thermal oxidation method or the like, and then photolithography is performed. Method and dry etching method are applied to remove the silicon oxide film in a predetermined portion to expose the single crystal silicon surface in that portion, and the n ⁻ -type single crystal silicon substrate 1 is etched using the silicon oxide film as a mask to make a shallow surface. Form a step.
Then, after removing the silicon oxide film used as the mask, the insulating film 2 is formed to have a uniform film thickness on the surface where the shallow step is formed (FIG. 9A).

Next, the insulating film 2 which is the convex portion of the step portion is removed by grinding, polishing, etching or the like, and the exposed surface of the single crystal silicon of the n ^-- type single crystal silicon substrate 1 and the insulating film 2 are removed.
To make the surface almost flat.

Next, the polycrystalline silicon layer 13 is formed by the CVD method or the like. This polycrystalline silicon layer 13 is replaced by XX
The surface is polished to a mirror surface (FIG. 9 (b)).

The flat surface obtained as described above and the main surface of the other n ^-- type single crystal silicon substrate 1 are bonded and heat-treated to obtain a single strongly bonded composite substrate (FIG. 9 (c)).

Next, the n ^-- type single crystal silicon substrate 1 is ground and polished up to the YY plane of FIG. 9C to make the silicon substrate have a desired thickness and the surface is flattened to obtain the single crystal silicon. The active layer 5 is formed. After that, an insulating film is formed on the flat surface, and the insulating film is formed into a required pattern by a photoetching method, and using this as a mask, alkali etching is performed to form a separation groove for element separation. The formation region and the control circuit element formation region are separated, and the single crystal silicon active layer 5 in the control circuit element formation region is divided into single crystal silicon islands 9.

[0016] Then, n by thermal oxidation or low-temperature CVD like ^-
An insulating film 10 made of SiO ₂ or the like is formed on the surface of the mold single crystal silicon substrate 1, and then a polycrystalline silicon layer 11 is formed by a CVD method. Then, the polycrystalline silicon layer 11 and the insulating film 10 on the surface of the substrate are removed by grinding / polishing or etching, while the isolation groove is filled with the insulating film 10 and the polycrystalline silicon layer 11 to insulate the element formation regions from each other. An SOI substrate is obtained (FIG. 9 (d)).

[0017]

In the first conventional example described above, single crystal silicon and an insulating film are mixed on one bonding surface of an SOI substrate, and such foreign materials are mixed. When flattening a surface, it is extremely difficult to suppress the step difference of the surface to 10 nm or less by the current polishing or etching technology. Therefore, the flatness of the bonding surface is insufficient and a void (unbonded portion) is generated on the bonding surface. As a result, peeling occurs in the void portion during the subsequent heat treatment, which causes a problem that, for example, the vertical power element cannot function.

Further, in the second conventional example, voids are unlikely to occur, but there is a drawback that the cost is increased because the steps of forming and polishing the polycrystalline silicon layer are increased.

An object of the present invention is to provide a semiconductor substrate having a structure in which no void is generated on the bonding surface in the region where the vertical power element is formed, and a method for manufacturing the semiconductor substrate.

[0020]

In order to achieve the above object, a semiconductor substrate according to the present invention comprises at least a pair of semiconductor substrates.
A semiconductor substrate obtained by closely bonding each of a plurality of semiconductor substrates with a mirror-polished surface as a bonding surface, wherein one semiconductor substrate of the pair has an insulating layer on a part of a main surface serving as the bonding surface. The insulating layer is provided at a position receding from the main surface of the semiconductor substrate.

A void is formed between the insulating layer and the bonding surface of the other semiconductor substrate forming the pair.

The semiconductor substrate according to the present invention is a semiconductor substrate in which at least two semiconductor substrates forming a pair are intimately bonded to each other with the mirror-polished surfaces as bonding surfaces, and one semiconductor substrate forming the pair is A part of the insulating layer is provided at a position receding from the main surface of the front semiconductor substrate, and another part of the insulating layer is provided. Is one that is in close contact with the main surface of the front semiconductor substrate.

Further, a cavity is formed in a part between the insulating layer and the bonding surface of the other semiconductor substrate forming the pair.

The pair of semiconductor substrates have a single crystal structure.

The method of manufacturing a semiconductor substrate according to the present invention comprises an insulating layer forming step, a surface layer processing step, a joining step,
A method of manufacturing a semiconductor substrate, comprising: a grinding / polishing step, wherein at least two semiconductor substrates forming a pair are closely bonded to each other with their respective mirror-polished surfaces as bonding surfaces to manufacture a semiconductor substrate. , A process of partially embedding an insulating layer on one main surface of one of the pair of semiconductor substrates, and the surface layer processing step is a step of processing the surface layer portion of the insulating layer to pull it from the main surface of the semiconductor substrate. In the bonding step, the surface layer portion of the insulating layer is retracted to a position retracted from one main surface of the semiconductor substrate, and the bonding step is performed on one of the semiconductor substrates in which the insulating layer is embedded. A process of joining one main surface and the mirror-polished surface of the other semiconductor substrate,
The grinding / polishing process is a process of grinding / polishing the one semiconductor substrate to form a polymerized semiconductor substrate.

The semiconductor substrate manufacturing method according to the present invention comprises an insulating layer forming step, a surface treatment step, a joining step,
A method of manufacturing a semiconductor substrate, comprising: a grinding / polishing step, wherein at least two semiconductor substrates forming a pair are closely bonded to each other with their respective mirror-polished surfaces as bonding surfaces to manufacture a semiconductor substrate. , A process of partially embedding an insulating layer on one main surface of one of the pair of semiconductor substrates, and the surface layer processing step is a step of processing the surface layer portion of the insulating layer to pull it from the main surface of the semiconductor substrate. In the bonding step, a part of the surface layer portion of the insulating layer is retracted to a position retracted from one main surface of the semiconductor substrate, and the remaining portion of the surface layer portion of the insulating layer is included. Is adhered to the other semiconductor substrate, the one main surface of the semiconductor substrate in which the insulating layer is embedded, and the mirror-polished surface of the other semiconductor substrate is a process of bonding, the grinding and polishing step, Grind and polish one of the semiconductor substrates A process of forming a semiconductor substrate engaged.

The joining step is a treatment performed in an oxygen atmosphere.

When the vertical power device and the control circuit device are monolithically integrated by using the two-layered semiconductor substrate according to the present invention, the bonding of the region where the vertical power device is formed is flat. Because it is done between different faces,
No void (unbonded portion) is generated on the bonding surface in the region where the vertical power element is formed, and as a result, the characteristics of the vertical power element are not deteriorated.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 and 3 are sectional views for explaining Embodiment 1 of the present invention in the order of steps. Figure 2
It is a top view showing a semiconductor substrate in the middle of manufacture.

As shown in FIG. 3, the semiconductor substrate according to the present invention has a basic structure in which at least two semiconductor substrates 1 and 4 forming a pair are closely bonded to each other with their mirror-polished surfaces as bonding surfaces. One semiconductor substrate 1 forming a pair
Has an insulating layer (insulating film) 2 on a part of the main surface serving as the bonding surface, and the insulating layer 2 is provided at a position receding from the main surface of the semiconductor substrate 1.

The semiconductor substrate manufacturing method according to the present invention for manufacturing the semiconductor substrate shown in FIG. 3 has an insulating layer forming step, a surface layer processing step, a bonding step, and a grinding / polishing step as a basic configuration. are doing. The processing contents of each step are as follows.

The insulating layer forming step is a step of forming the insulating layer 2 by partially embedding it in one main surface of the pair of semiconductor substrates 1. In the surface layer processing step, the surface layer portion of the insulating layer 2 is formed. It is a process of processing and retracting the semiconductor substrate 1 to a position retracted from one main surface.

In the bonding step, the main layer of one of the semiconductor substrates 1 in which the insulating layer 2 is embedded is left with the surface layer portion of the insulating layer 2 retracted to the position retracted from the main surface of the semiconductor substrate 1. The surface is joined to the mirror-polished surface of the other semiconductor substrate 4, and the grinding / polishing step is a process of grinding / polishing the one semiconductor substrate 1 to form polymerized semiconductor substrates 1 and 4. is there.

Next, an n ⁻ type single crystal silicon substrate is used as the semiconductor substrate 1 and an n ⁺ type single crystal silicon substrate is used as the semiconductor substrate 4, respectively, which is optimum for monolithically integrating the vertical power device and the control circuit device. The manufacturing method of the present invention will be described in the order of steps taking a semiconductor substrate as an example.

As shown in FIG. 1A, an n ⁻ type single crystal silicon substrate 1 having a diameter of 5 inches, a thickness of about 600 μm and a resistivity of about 1 Ωcm is prepared. Next, as shown in FIGS. 1A and 2, an insulating film (insulating layer) having a thickness of about 2 μm is formed on a part of one main surface of the n ⁻ -type single crystal silicon substrate 1 by a selective oxidation (LOCOS) method. Form 2. 2 is a plan view showing the n ⁻ -type single crystal silicon substrate 1, and FIG. 1 (a) is a sectional view taken along the line AA of FIG.

Then, as shown in FIG. 1B, the insulating film 2 is thinned to a thickness of 0.8 μm with an HF-based etching solution,
The surface of the insulating film 2 is made lower than the bonding surface 1a of the single crystal silicon substrate 1, that is, the surface of the insulating film 2 is retracted to a position retracted from the bonding surface (one main surface) 1a of the silicon substrate 1.

Next, as shown in FIG. 1C, the diameter is 5 inches, the thickness is about 600 μm, and the resistivity is about 0.01 to 0.02 Ω.
cm n ⁺ type single crystal silicon substrate 4 is prepared, and insulating film 2
While the surface layer part of the semiconductor substrate 1 is retracted to the position retracted from the main surface of the semiconductor substrate 1, the bonding surface 4a of the n ⁺ type single crystal silicon substrate 4 and the insulating film 2 on the n ⁻ type single crystal silicon substrate 1 are formed. The bonded surface 1a is bonded to each other in the atmosphere at room temperature. Note that the bonding may be performed in an oxygen atmosphere. After that, in order to strengthen the joint, 1100 to 120
Heat treatment is performed at 0 ° C. for about 2 hours. When the substrates 1 and 4 are bonded, a cavity 3 having a thickness of 0.2 μm is formed between the surface layer portion of the insulating layer 2 and the bonding surface 4 a of the substrate 4. In addition,
The thickness of the cavity 3 may be about 0 to 0.5 μm by adjusting the etching amount of the insulating film 2.

After that, as shown in FIG.
The n ⁻ -type single crystal silicon substrate 1 is ground and polished to the YY plane of (c) to make the silicon substrate 1 have a desired thickness and the surface is flattened, and the single crystal silicon active layer 5 is formed on the substrate 1. Form. Next, as shown in FIG. 3B, a silicon oxide film having a uniform thickness is formed on the single crystal silicon active layer 5 by a thermal oxidation method or a CVD method, and the silicon oxide film is patterned. The unnecessary silicon oxide film is removed. Next, isolation trenches 6 for element isolation are formed in a part of the single crystal silicon active layer 5 by alkali etching or reactive ion etching (RIE) using the patterned silicon oxide film as a mask,
The single crystal silicon active layer 5 is separated into the vertical power element formation region 7 and the control circuit element formation region 8 by the separation groove 6, and the single crystal silicon active layer 5 in the control circuit element formation region 8 is formed on the insulating layer 2. Divide into single crystal silicon islands 9. After that, the silicon oxide film used as the mask is removed.

Next, as shown in FIG. 3C, an insulating film 10 made of SiO ₂ or the like is formed on the entire surface of the n ⁻ type single crystal silicon substrate 1 by thermal oxidation or low temperature CVD, and then C
The polycrystalline silicon layer 11 is formed in the isolation trench 6 by the VD method. Thereafter, the polycrystalline silicon layer 11 and the insulating film 10 on the surface of the silicon substrate 1 are removed by grinding / polishing or etching, while the isolation groove 6 is filled with the insulating film 10 and the polycrystalline silicon layer 11 to form each element. An SOI substrate in which the formation regions are isolated from each other is obtained.

(Embodiment 2) FIG. 4 is a vertical sectional view for explaining Embodiment 2 of the present invention in the order of steps. FIG.
The single crystal silicon active layer 5 is formed by grinding and polishing from the non-bonded surface of the bonded substrate shown in (c) (FIG. 4).
(A)). Then, a photolithography method is applied to form a photoresist pattern, which is used as a mask to inject boron at a high concentration to form a P ⁺ -type isolation region 12 (FIG. 4B). From this, the vertical power element formation region 7
And the control circuit element forming region 8 and the single crystal silicon active layer 5 in the control circuit element forming region 8 is divided into single crystal silicon islands 9 on the insulating layer 2.

In the second embodiment, the vertical power element forming region 7 is formed.
This is applicable when the withstand voltage between the control circuit element region 8 and the control circuit element region 8 may be low, and the element isolation step using the isolation groove 6 as in the case of the first embodiment can be omitted. Can be simplified.

(Embodiment 3) FIGS. 5 and 6 are sectional views illustrating Embodiment 3 of the present invention in the order of steps. In FIG. 6, the semiconductor substrate according to the present invention is basically a semiconductor substrate in which at least two semiconductor substrates 1 and 4 forming a pair are closely bonded to each other with their mirror-polished surfaces as bonding surfaces.
On the other hand, the semiconductor substrate 1 forming a pair has an insulating layer (insulating film) 2 on a part of the main surface serving as the bonding surface, and the part 2a of the insulating layer 2 is the main surface of the semiconductor substrate 1. The other portion 2b of the insulating layer 2 provided at a position retracted from
Are in close contact with the main surface of the semiconductor substrate 4.

The semiconductor substrate manufacturing method according to the present invention for manufacturing the semiconductor substrate shown in FIG. 6 has an insulating layer forming step, a surface treatment step, a bonding step, and a grinding / polishing step as a basic configuration. are doing. The processing contents of each step are as follows.

The insulating film forming process is a process of partially embedding the insulating layer 2 on one main surface of the pair of semiconductor substrates 1, and the surface treating process forms the surface layer of the insulating layer 2. This is a process in which the semiconductor substrate 1 is processed and retracted to a position retracted from one main surface of the semiconductor substrate 1. At this time, the surface layer portion of the insulating layer 2 is processed to have a depth of 0.1 μm or less so that the surface portion of the insulating layer 2 is set back from the main surface of the semiconductor substrate 1 to a retracted position.

In the joining step, a part 2a of the surface layer portion of the insulating layer 2 is set back to a position retracted from one main surface of the semiconductor substrate 1, and the remaining part 2b of the surface layer portion of the insulating layer 2 is used as a partner. This is a process of bringing one main surface of the one semiconductor substrate 1 in which the insulating layer 2 is embedded and the mirror-polished surface of the other semiconductor substrate 4 into close contact with the semiconductor substrate 4 on the side, and the grinding / polishing step is performed. A process of grinding and polishing the one semiconductor substrate 1 to form superposed semiconductor substrates 1 and 4.

Next, an n ⁻ -type single crystal silicon substrate is used as the semiconductor substrate 1 and an n ⁺ -type single crystal silicon substrate is used as the semiconductor substrate 4, respectively, which is optimal for monolithically integrating the vertical power device and the control circuit device. The manufacturing method of the present invention will be described in the order of steps taking a semiconductor substrate as an example.

As shown in FIG. 5A, an n ⁻ -type single crystal silicon substrate 1 having a 5-inch system, a thickness of about 600 μm, and a resistivity of about 1 Ωcm is prepared. Next, as shown in FIGS. 5A and 2, an insulating film (insulating layer) having a thickness of about 2 μm is formed on a part of one main surface of the n ⁻ -type single crystal silicon substrate 1 by a selective oxidation (LOCOS) method. Form 2.

Next, as shown in FIG. 5B, the insulating film 2 is thinned to a thickness of 0.9 with an HF-based etching solution, and the surface of the insulating film 2 is separated from the bonding surface 1a of the single crystal silicon substrate 1 by using the bonding surface 1a. Is also lowered, that is, the surface of the insulating film 2 is retracted to a position retracted from the bonding surface (one main surface) 1a of the silicon substrate 1.

Next, as shown in FIG. 5C, the diameter is 5 inches, the thickness is about 600 μm, and the resistivity is about 0.01 to 0.002.
An n ⁺ type single crystal silicon substrate 4 of Ωcm is prepared, and a bonding surface 4a of the n ⁺ type single crystal silicon substrate 4 and a bonding surface 1a on which the insulating film 2 on the n ⁻ type single crystal silicon substrate 1 is formed. Are bonded to each other in the air at room temperature. The joining may be performed in an oxygen atmosphere. When the substrates 1 and 4 are faced to each other and the bonding process is performed, a cavity 3 having a thickness of 0.1 μm is secured between the insulating layer 2 and the bonding surface 4a of the substrate 4. At this time, the thickness of the cavity 3 is 0 to 0.12 μm by adjusting the etching amount of the insulating film 2.
Need to be

To strengthen the bond, heat treatment is performed at 1100 ° C. to 1200 ° C. for about 2 hours. By this heat treatment, as shown in FIG. 5D, the central portion 2 of the insulating film 2 is
b is closely bonded to the bonding surface 4a of the substrate 4, the peripheral portion 2a of the insulating film 2 remains retracted away from the bonding surface 4a of the substrate 4, and the cavity 3 corresponds to the peripheral portion 2a of the insulating film 2. It remains only in the part you do.

After that, as shown in FIG.
The n ⁻ -type single crystal silicon substrate 1 is ground and polished up to the YY plane of (d) to make the n ⁻ -type single crystal silicon substrate 1 have a desired thickness and the surface thereof is flattened. A silicon active layer 5 is formed.

Next, as shown in FIGS. 6B and 6C, the isolation trench 6 for element isolation is formed in a part of the single crystal silicon active layer 5 as in the first embodiment, and the single crystal silicon active layer 5 is formed. The layer 5 is separated into a vertical power element formation region 7 and a control circuit element formation region 8 by a separation groove 6, and the control circuit element formation region 8 is formed.
The single crystal silicon active layer 5 in is divided into single crystal silicon islands 9 on the insulating layer 2. Then, as in the first embodiment, the isolation trench 6 is filled with the insulating film 10 and the polycrystalline silicon layer 11, and the SOI in which the element formation regions are insulated and separated from each other.
Get the substrate.

In the embodiment shown in FIGS. 5 and 6,
The element forming regions are insulated and isolated by using the isolation groove 6, but as shown in FIG. 7, the P ⁺ type isolation regions 12 are formed and the element forming regions are insulated and isolated as in the second embodiment. Good.

In the third embodiment, the central portion 2b of the insulating film 2 is
Is bonded to the bonding surface 4a of the substrate 4, the thermal conductivity from the insulating film 2 to the mating substrate is better than that of the SOI substrates of the first and second embodiments, and the control circuit element region 8
It is possible to prevent malfunction of the control element formed in the above due to a temperature rise, and to increase the mechanical strength of the control circuit element region 8.

[0056]

As described above, the present invention, when applied to a semiconductor substrate for monolithically integrating a vertical power device and a control circuit device, attaches a region where a vertical power device is formed. Since the alignment is performed between flat single crystal silicon surfaces, no void (unbonded portion) is generated on the bonding surface in the region where the vertical power element is formed, and as a result, the characteristics of the vertical power element are deteriorated. It can be prevented from occurring. Therefore, according to the present invention, it is possible to provide a highly reliable power IC.

Further, since there is no step of forming and polishing the polycrystalline silicon layer, the substrate manufacturing cost can be kept low.

Further, since a part of the insulating layer is bonded to the mating semiconductor substrate, the thermal conductivity from the insulating layer to the mating semiconductor substrate is good and the temperature rise of the control element formed in the control circuit element region. It is possible to prevent the malfunction due to the above, and to increase the mechanical strength of the control circuit element region.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the method of manufacturing a semiconductor substrate according to the first embodiment of the present invention in the order of steps.

FIG. 2 is a plan view showing the substrate in the process of the method for manufacturing the semiconductor substrate according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the method of manufacturing the semiconductor substrate according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view for explaining the method of manufacturing the semiconductor substrate according to the second embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view for explaining the method of manufacturing the semiconductor substrate according to the third embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view for explaining the method of manufacturing the semiconductor substrate according to the third embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view for explaining a case of applying the method for manufacturing a semiconductor substrate shown in FIG. 4 to a method for manufacturing a semiconductor substrate according to a third embodiment of the present invention in the order of steps.

FIG. 8 is a cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 9 is a cross-sectional view for explaining another manufacturing method of the conventional example.

[Explanation of symbols]

1 n ⁻ Type Single Crystal Silicon Substrate 2, 10 Insulation Film 3 Cavity 4 n ⁺ Type Single Crystal Silicon Substrate 5 Single Crystal Silicon Active Layer 6 Separation Groove 7 Vertical Power Element Forming Area 8 Control Circuit Element Forming Area 9 Single Crystal Silicon Island 11, 13 Polycrystalline silicon layer 12 P ⁺ type isolation region

Claims (8)

[Claims] 1. A semiconductor substrate in which at least two semiconductor substrates forming a pair are intimately bonded to each other with a mirror-polished surface as a bonding surface, and one of the pair of semiconductor substrates serves as the bonding surface. A semiconductor substrate having an insulating layer on a part of the surface thereof, wherein the insulating layer is provided at a position retracted from the main surface of the semiconductor substrate. 2. The semiconductor substrate according to claim 1, wherein a gap is formed between the insulating layer and the bonding surface of the other semiconductor substrate forming the pair. 3. A semiconductor substrate in which at least two semiconductor substrates forming a pair are closely bonded to each other with a mirror-polished surface being a bonding surface, and one semiconductor substrate forming the pair is a main surface serving as the bonding surface. A part of the insulating layer is provided at a position receding from the main surface of the semiconductor substrate, and the other part of the insulating layer is a main part of the semiconductor substrate. A semiconductor substrate, which is in close contact with the surface. 4. The semiconductor substrate according to claim 3, wherein a cavity is formed in a part between the insulating layer and the bonding surface of the other semiconductor substrate forming the pair. 5. The semiconductor substrate according to claim 1, wherein the pair of semiconductor substrates has a single crystal structure. 6. An insulating layer forming step, a surface layer treating step, a joining step, and a grinding / polishing step, wherein at least two semiconductor substrates forming a pair are closely joined to each other with their mirror-polished surfaces as joint surfaces. In the method for manufacturing a semiconductor substrate, the insulating layer forming step is a step of partially embedding an insulating layer on one main surface of one of the paired semiconductor substrates. Is a process of processing the surface layer portion of the insulating layer to recede to a position retracted from the one main surface of the semiconductor substrate, and the bonding step includes retracting the surface layer portion of the insulating layer from the one main surface of the semiconductor substrate. The process of joining one main surface of the one semiconductor substrate in which the insulating layer is embedded and the mirror-polished surface of the other semiconductor substrate with the insulating layer being buried is performed. Polymerization by grinding and polishing semiconductor substrates The method of manufacturing a semiconductor substrate, characterized in that the a process for forming a semiconductor substrate. 7. An insulating layer forming step, a surface layer treating step, a joining step, and a grinding / polishing step, wherein at least two mirror-polished surfaces of two semiconductor substrates forming a pair are closely bonded to each other as bonding surfaces. In the method for manufacturing a semiconductor substrate, the insulating layer forming step is a step of partially embedding an insulating layer on one main surface of one of the paired semiconductor substrates. Is a process of processing the surface layer portion of the insulating layer to recede to a position retracted from the one main surface of the semiconductor substrate, and the bonding step is a step of removing a part of the surface layer portion of the insulating layer from the one main surface of the semiconductor substrate. From the main surface of the one semiconductor substrate in which the insulating layer is embedded, and the other semiconductor substrate by adhering the remaining portion of the surface layer portion of the insulating layer to the other semiconductor substrate. This is the process of joining the mirror-polished surface of The method of manufacturing a semiconductor substrate, wherein the grinding / polishing step is a process of grinding / polishing the one semiconductor substrate to form a polymerized semiconductor substrate. 8. The method for manufacturing a semiconductor substrate according to claim 6, wherein the joining step is a treatment performed in an oxygen atmosphere.