JPH01149449A - Cmos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To inhibit the generation of a hot carrier effect and to improve a mutual conductance by a method wherein a CMOS semiconductor device is constituted in a structure, wherein low-concentration source and drain regions are respectively interposed between a channel region and a high-concentration source region and between the channel region and a high-concentration drain region in an n-channel element and the inside end surfaces in high-concentration source and drain regions are directly connected to a channel region in a p-channel element. CONSTITUTION:In an n-MOS transistor, wherein hot carriers are easy to generate, n<-> source and drain regions 14A and 14B having a high resistance are respectively interposed between an n<+> source region 15A and a channel region ch1 under the lower part of a first gate electrode 12A and between an n<+> drain region 15B and the channel region ch1. Poly Si sidewalls 13A and 13B connected directly to the electrode 12A are arranged on the upper parts of these regions 14A and 14B through a gate oxide film 11, the regions 14A and 14B are turned into an n-type more intensely by the sidewalls 13A and 13B, which become the same potential as that of the electrode 12A, at the time of operation and their resistance values are reduced. Moreover, p<+> source and and drain regions 16A and 16B of a p-MOS transistor are directly connected to a channel region ch2.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment Schematic side cross-section of an embodiment of the present invention ( FIG. 1) Process sectional view of an embodiment of the method of the present invention (FIG. 2) Effects of the invention [Summary] CMOS semiconductor device and manufacturing method thereof, particularly structure and manufacturing method of CMOS semiconductor device to be short-channeled The purpose of this invention is to provide a structure and manufacturing method thereof that suppresses the occurrence of hot carrier effects and improves the gm of n-channel and p-channel devices. a first gate electrode disposed through a conductor sidewall formed in direct contact with both side surfaces of the first gate electrode, and a lower region of each sidewall in the p-wall region; A first n-type source region and a first n-type drain region each having a low impurity concentration are arranged individually, and an inner end surface of the p-wall region is formed into a first n-type source region and a first n-type drain region, respectively. an n-channel MIS transistor having a second n-type source region and a second n-type drain region having a high impurity concentration and disposed in contact with an outer end surface of the n-type drain region;
a second gate electrode disposed on the type region via a gate insulating film; and a high impurity concentration disposed in the n-type region with an inner end surface in contact with a lower region of the second gate electrode. p
A CMOS semiconductor device constituted by a p-channel MISI transistor having a p-type source region and a p-type drain region, and a manufacturing method using self-alignment means.

[Industrial application field]

The present invention relates to a CMOS semiconductor device and a method of manufacturing the same, and particularly to improvements in the structure and method of manufacturing a CMOS semiconductor device that is short-channeled.

In 0MO3IC, which is becoming highly integrated and large-scale,
In order to compensate for the decrease in operating speed due to reduction in wiring width and increase in wiring length, short channelization is being promoted.

As MOS FETs become increasingly short-channeled and the distance between the source and drain decreases, the resulting increase in the electric field strength between the source and drain generates hot carriers with high energy in the channel region. The real carriers penetrate into the gate insulating film due to their high energy and are accumulated, and over time the MOS F
There is a problem of changing the dark value voltage of the ET and lowering the gm (mutual conductance).

Therefore, as a means to reduce the electric field strength between the source and drain and suppress the generation of hot carriers, a low impurity concentration source and drain region is interposed between the channel region and a high impurity concentration source and drain region.
A CMOS semiconductor device with a D (Lightly Doped Drain) structure has been proposed, but this LD
In a D-structure CMOS semiconductor device, the gm (mutual conductance) of the n-channel element and the p-channel element decreases because the low impurity concentration source and drain regions provided to prevent the hot carrier effect have a high resistance value.
There is a problem in that it is not possible to increase the speed of the CMOS semiconductor device, which limits the speeding up of the CMOS semiconductor device, and an improvement is desired.

[Conventional technology]

A conventional short channel CMOS semiconductor device with an LDD structure As shown in FIG. 3(a), a p-type well 2 and an n-type well 3 are formed in a p-type silicon substrate 1, for example.
A normal substrate to be processed in which at least an n-channel element formation region 8 and an n-channel element formation region 9 are individually exposed by openings in a field oxide film 6 having a p-type channel stopper 4 or an n-type channel stopper 5 at the bottom thereof. After first forming a gate insulating film 11 on the silicon exposed surface using Next, the n-channel element forming region 8 and the n-channel element forming region 9 are alternately covered with resist films (not shown), and using the gate electrode as a mask, an n-type impurity such as phosphorus (P) and an n-type impurity such as boron (B) are applied. ) is selectively introduced at a low concentration to form n-type source and drain regions 51A and 51B with a low impurity concentration in the n-channel element forming region 8, the inner end surfaces of which are self-aligned with the side surfaces of the first gate electrode 12A. a low impurity concentration p-type source and drain region 52A whose inner end surface is self-aligned with the side surface of the second gate electrode 12B in the n-channel element formation region 9;
52B is formed.

Next, after removing the exposed gate insulating film 11 and forming a thin silicon dioxide (SiOz) film 53 on the silicon exposed surface, a vapor phase growth (CVD) insulating film is formed on the substrate, and an anisotropic dry etching means is applied. As shown in FIG. 3(b), the first and second gate electrodes are etched back.
Insulating film sidewall 54A on the side of 1x2A, 12B
and 54B, and then an n-channel element forming region 8
and a first or second gate electrode 12A that alternately covers the n-channel element forming region 9 with a resist film (not shown) and has the insulating film sidewall 54A or 54B,
12B as a mask, an n-type impurity such as arsenic (As'') and an n-type impurity such as B'' are selectively introduced at a high concentration, so that the inner end surface is covered with the insulating film side walls 54A, 5.
A method was used to form highly impurity-concentrated n° type source and drain regions 55A and 55B and p′ type source and drain regions 56A and 56B, which were self-aligned with the outer end face of 4B.

[Problem that the invention seeks to solve]

Therefore, in a CMOS device with a conventional LDD structure, n
channel device (n-MOS) and p-channel device (p-
MOS), an insulating film sidewall is formed on the side surface of the gate electrode, and a highly doped n-type source and drain region 5 is formed.
58 and 55B, and p+ type source and drain regions 56
A and 56B are both formed in self-alignment with the outer end surface of the insulating film sidewall, and the electrodes 12A, 12
Lower channel regions 57, 58, etc. of B, etc. and source and drain regions 55A, 55B, 56A with high impurity concentration
, 56B, etc., all have low impurity concentration source and drain regions 51A, 51B, 52A and high resistance.
, 52B, etc., an n-channel element (n-Tr) and a p-channel element (p-Tr)
It is not possible to obtain a high grn for both C and C.
A problem has arisen in that the operating speed of the MOS semiconductor device decreases.

Therefore, the present invention suppresses the occurrence of the hot carrier effect, and
Another object of the present invention is to provide a structure of a short channel CMO8 semiconductor device and a method for manufacturing the same, which realizes improvement in gm of an n-channel device and a p-channel device.

[Means for solving problems]

The above problem is caused by a first gate electrode disposed on the n-type region with a gate insulating film interposed therebetween, and conductive sidewalls formed in direct contact with both side surfaces of the first gate electrode. A first n-type source region and a first n-type drain region each having a low impurity concentration are individually disposed in a lower region of each sidewall in the n-type region, and an inner end surface is provided in the n-type region. and a second n-type source region and a second n-type drain region having a high impurity concentration and disposed in contact with the outer end surfaces of the first n-type source region and the first n-type drain region, respectively. n-channel MfSl-
a transistor, a second gate electrode disposed on the n-type region with a gate insulating film interposed therebetween; A CMOS semiconductor device according to the present invention comprising a p-channel MISt-transistor having a p-type source region and a p-type drain region having an impurity concentration, and an n-type region and an n-type region serving as an element formation substrate. and a first region defining and expressing an element formation region and a contact formation region of the p-type substrate and an element formation region and a contact formation region of the n-type substrate.
, forming a gate insulating film on the semiconductor substrate exposed in each of the openings of the semiconductor processing substrate on which the field insulating film having second, third, and fourth openings is formed; forming a first conductive film having a first insulating film on the top surface on the substrate to be processed; patterning the first conductive film in alignment with a first mask; a first gate electrode extending over the first opening and having a first insulating film on the upper surface; a third opening; covering the second opening and having the first insulating film on the upper surface; forming first and second covering patterns; and introducing a first n-type impurity through a first opening in the field insulating film using the first gate electrode as a mask; forming n-type low impurity concentration source and drain regions whose inner end surfaces are self-aligned with each side surface of the electrode; forming a second conductive film on the substrate; and forming a second conductive film on the substrate; forming second conductive film sidewalls on both sides of the first gate electrode by performing etch hack;
A second n-type impurity is introduced through the opening using the first gate electrode having the sidewall as a mask, so that the inner end surface is self-aligned with the outer end surface of each sidewall.
forming source and drain regions with high impurity concentration, and introducing the second n-type impurity through the fourth opening to form a base contact region with high impurity concentration; and a second mask. a first resist pattern corresponding to the second gate electrode is formed on the first coating pattern in alignment with the first resist pattern, and second and fourth resist patterns covering the first and fourth openings of the field insulating film are formed. forming a second gate electrode over the third opening of the field insulating film by selectively etching and removing the first covering pattern using the first resist pattern as a mask; and etching away the second covering pattern, and introducing an n-type impurity into the second gate electrode through the third opening of the field insulating film using the second gate electrode as a mask. P-wall high impurity concentration source and drain regions whose inner end surfaces are self-aligned are formed on each side of the electrode, and the n-type impurity is introduced through the second opening to form a p-type high impurity concentration substrate contact region. The problem is solved by a method of manufacturing a CMO8 semiconductor device according to the present invention, which includes a step of forming a CMO8 semiconductor device.

[For production]

That is, in the present invention, an n-channel device in which hot carriers are likely to be generated because the carriers are light-weight electrons has a source and drain region with a low impurity concentration between the channel region and a source and drain region with a high impurity concentration. This reduces the electric field strength formed between the source and drain to limit the generation of hot carriers, and at the same time, a conductive side wall is provided above the low impurity concentration source and drain regions having high resistance in contact with the gate electrode. By applying the same potential as the gate to the conductive sidewall, the source and drain regions with low impurity concentration are further strengthened.
A p-channel device improves gm by lowering the resistance by forming a p-channel device, and is less likely to generate hot carriers because the carriers are heavy holes. A short channel CMOS semiconductor device is provided which improves gm by arranging them in direct contact with each other, thereby preventing characteristic fluctuations due to photocarriers and improving operating speed.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view showing a main part of an embodiment of the structure according to the present invention, and FIGS. 2(a) to (gl) are process sectional views of an embodiment of the method according to the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

The short channel CMOS semiconductor device according to the present invention includes:
For example, as shown in FIG.
For example, an n-type transistor having high conductivity is formed on the n-channel element formation region 8 of the p-type well 2 with an impurity concentration of about 10 IscJ-3 defined by A first gate electrode 12A with a width of about 1 μm formed of packed crystal silicon, and a thickness of about 2000 to 3000 formed on both sides of the gate electrode 12Δ are ohmically connected to the deformed gate electrode 12A. N+ type polycrystalline silicon sidewalls 13A and 13B which are in contact with and whose lower surfaces are in contact with the gate oxide film 11, and lower regions of the polycrystalline silicon sidewalls 13A and 13B of the p-type upper L are disposed. The inner end portion is self-aligned with the side surface of the gate electrode 12A, and l Q I 7
The n-type source region 14A and n-type drain region 14B having a low impurity concentration of about cm -3 and the inner end portions disposed in the outer regions thereof are the outer ends of the polycrystalline silicon sidewalls 13A and 1313. An n-channel MO3 transistor (n-M
OS), and the n-type transistor is formed on the p-channel element forming region 9 of the n-type well 2 with an impurity concentration of about IQ"cm-3 defined and exposed by the field oxide film 6 via the gate oxide film 11. a second gate electrode 12B made of packed crystalline silicon;
The p source regions 16A and p source regions 16A and 16A having a high impurity concentration of about 19200 m-3 are arranged in the n-type well 2 and whose inner end surfaces are self-aligned with the side surfaces of the second gate electrode 12B.
It is provided with a p-channel MOS transistor (p-MOS) configured to include a ゛-type drain region 16B.

In FIG. 1, 1 is a p-type silicon substrate, 4 is a p-type silicon substrate, and 4 is a p-type silicon substrate.
type channel stopper, 5 indicates an n type channel stopper. Furthermore, the structures of the interlayer insulating film, metal wiring, etc., which are not shown, are the same as those of the prior art.

As mentioned above, in the CMOS semiconductor device according to the present invention, the n-channel MO3I-
The transistor (n-MOS) has a high concentration source region 15A and n
A low concentration layer having high resistance, that is, n-
A gate oxide film 11 is provided above the n-type source region 14A and the n-type drain region 14B.
Polycrystalline silicon sidewalls 138 and 13B are provided which are directly connected to the gate electrode 12A through the gate electrode 12A. The source region 14A and the n-type drain N region 1413 are more strongly converted to n-type, and their resistance value is reduced, so that gm is improved.

Also p-channel MO3 transistor (p-1'1O3)
That is, the p' source region 16A and the p' type drain region 16B are in direct contact with the channel region chz.
Its gm is made high enough.

Next, a CMOS semiconductor device according to the present invention that can easily form a CMOS semiconductor device having the structure according to the present invention in a short order
A method for manufacturing a MOS semiconductor device will be described below with reference to process cross-sectional views.

FIG. 2 (see al) For example, a p-type silicon substrate 1, a p-type well 2 and an n-
A type well 3 is formed, and a p-type channel stopper 4 is formed at the bottom.
Alternatively, at least the p-type well contact formation region 7, the n-channel element formation region 8, the p-channel element formation region 9, and the n-well contact formation region 10 are individually defined by openings in the field oxide film 6 having the n-type channel stopper 5. Using a conventional twin-tub structure workpiece substrate, a gate oxide film 11 having a thickness of approximately 200 mm is formed on the exposed silicon surface of the substrate in the same manner as in the conventional method. A first polycrystalline silicon film 112 with a thickness of about 4,000 layers is formed by the CVD method, and phosphorus (P) is introduced at a high concentration by a method such as gas diffusion to give the polycrystalline silicon film 112 a high tetraelectricity. (n+ type), and then thermal oxidation or the like is applied to the polycrystalline silicon film 112 to a thickness of 50 mm.
A first SiO □ film (OXI) having a thickness of about 0 is formed.

Referring to FIG. 2(b), the polycrystalline silicon film 112 having the first SiO□ film (OXI) is patterned by ordinary photolithography using a first mask, and a first (polycrystalline silicon) gate electrode 12
A, a first (polycrystalline silicon) covering pattern 112B is formed on the p-channel element forming region 9, and a second (polycrystalline silicon) covering pattern 112C is formed on the p-well contact forming region 7.

Next, the gate electrode 12A, the covering pattern 112B,
Using 112C and field oxide film 6 as a mask, ions of Fi(P") are implanted at a low dose of about 101310l3 through gate oxide film 11. Through this ion implantation, the inner edge becomes the gate electrode in n-channel element forming region 8. Low concentration P input region 114 aligned with the side surface of 128 itself
A and 114B are formed, and a lightly doped P-type region 114C is formed in the n-well contact formation region IO.

Refer to FIG. 2(C).Next, a film with a thickness of 2000 to 300 mm is coated on the substrate by CVD method.
A second polycrystalline silicon film 113 of about 0.0 is formed, and then highly conductive (n+ type) is imparted to the polycrystalline silicon film 113.

FIG. 2 (see dl) Next, the second polycrystalline silicon film 113 is subjected to a reactive ion etching (RIE) process to expose the gate oxide film 11, the first Sin film (OXI), and the field oxide film 6. The entire surface is etched (etched back) until polycrystalline silicon sidewalls 13A and 13B remain on the side surfaces of the first gate electrode 12A. Although the sidewall 13C is formed, no particular problem occurs.

Next, the polycrystalline silicon sidewall 13A,
Using the first gate electrode 12A having a 13B diameter, the covering patterns 112B and 112C, and the field oxide film 6 as masks, phosphorus (As") is applied 4x through the gate oxide film 11.
Ion implantation is performed at a high dose of about 10+ S cm-Z.

By this ion implantation, the inner end portions of the n-channel element forming region 8 are made of polycrystalline silicon sidewalls 13A, 1.
High concentration As” implanted region 115 aligned with the outer end face of 3B
A and 115B are formed, and a high concentration As'' implantation region 115C is formed in the n-well contact formation region 10.

Refer to FIG. 2 Te) Then, by a second photo process using a second mask, a first pattern corresponding to the shape of the gate electrode of the p-channel device is formed on the first ring pattern 112B having the first 5iOz film OX+. At the same time as forming the resist pattern 17A, a second resist pattern 17B covering the n-channel element formation region 8 and a third resist pattern 17C covering the n-well contact region 10 are formed. Then, the first covering pattern 112B is patterned by ordinary RIE processing to form the gate electrode 12B of the p-channel device, and at the same time, the third covering pattern 112C is etched away. At this time, the sidewall 13G is also removed by etching.

Next, the gate electrode 12B1 having the first resist pattern 17A on top, the second resist pattern 17B, and the third resist pattern 17B are formed.
Using the resist pattern 17C and the field oxide film 6 as a mask, the IQIScm-Z
First and second high-concentration B+ implanted regions 116A are implanted with a relatively high dose of B, and the inner end portions of the p-channel element forming region 9 are aligned with the side surfaces of the gate electrode 12B itself.
116B, and a third high concentration B implantation region 116C is formed in the p-well contact formation region 7.

2 (see O) Next, after removing the resist patterns 17A, 17B, 17C, a predetermined heat annealing process is performed to form the low concentration P4 implanted regions 114A, 114B, 114c and the high concentration As' implanted regions 115A, 115B, 115C. and the high-concentration B degree implantation regions 1168, 116B, and 116C are activated, and an n-type source region 1 whose inner end surface is self-aligned with the side surface of the gate electrode 12A itself is formed in the n-channel element formation region 8.
48, n-type drain region 14B, and polycrystalline silicon sidewalls 134 and 13B on the sides of the gate electrode.
The n'-type source region 15A and the n"" type source region 148, whose inner end faces are self-aligned with the outer end faces of A source region 16A and a p'' type drain region 16B are formed, a p'' type well contact region 16C is formed in the p well contact forming region 7, and an n'' type well contact region 15G is formed in the n well contact forming region 1o.

Here, an n-type LDD structure having polycrystalline silicon sidewalls 13A and 13B in direct contact with the side surfaces of the gate electrode 12A are formed above the low-concentration source and drain regions, that is, the n-type source region 14A and the n-type drain region 14B. Channel M, 0SI-transistor (LDD-n-MOS) and p-channel MO3I-transistor (p-MO
S) is formed.

Note that this activation treatment may be performed simultaneously with heat treatment when reflowing the interlayer insulating film in a later step. .

After removing the thin first 5302 film OX and the gate oxide film 11 exposed after referring to FIG. 2(g), an SiO□ film 18 for impurity blocking is formed on the silicon exposed surface by thermal oxidation means,
Next, a PSG interlayer insulating film 19 is formed as usual, and a wiring contact window passing through the interlayer insulating film 19 and the impurity blocking SiO□ film 18 is formed to form an n-channel device (LDD-n-MOS) made of aluminum or the like. Gate wiring 20, source wiring 21, drain wiring 22, gate wiring 23 of p-channel element (p-MOS), source wiring 24
, the drain wiring 25, the p-well wiring 26, the n-well wiring 27, etc. are formed, and the short channel CMOS semiconductor device having the structure according to the present invention is completed.

Note that in the present invention, the gate electrode and the conductive sidewall are not limited to the polycrystalline silicon described above.

〔Effect of the invention〕

As explained above, according to the present invention, the short channel C
In a MOS semiconductor device, an n-channel MO3I-transistor, in which hot carriers are likely to be generated, has a lightly doped source and drain region interposed between a channel region and a highly doped source and drain region to reduce the electric field strength between the source and drain. A conductive side wall having the same potential as the gate electrode is disposed via a gate insulating film on the low concentration source and drain regions having high resistance and thereby weakening the hot carrier generation. Due to the potential of the sidewalls, the lightly doped source and drain regions become stronger (n-type) and have lower resistance.

Furthermore, a p-channel MOS transistor that generates almost no hot carriers even when the electric field strength between the source and drain is high is designed to improve gm by having a structure in which the inner end surfaces of the highly doped source and drain regions are in direct contact with the channel region.

Therefore, a CMOS semiconductor device is formed in which there is little change over time in the dark value voltage due to the accumulation of hot carriers in the gate insulating film, and the gm is relatively large. It is effective for

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view showing the essential parts of an embodiment of the structure according to the present invention, and FIGS. 2(a) to (g+ are of an embodiment of the method according to the present invention. p-type silicon substrate, 2 p-type well, 3 n-type well, 4 n-type channel stopper, 5 n-type channel stopper, 6 field oxide film, 7 n-well contact formation region, 8 n-channel element formation region, 9 p-channel element formation region, 10 n-well contact formation region, 11 gate oxide film, 12A and 12B gate electrode, 138, 13B polycrystalline silicon sidewall, 1
4A is an n-type source region, 14B is an n-type drain region, 15A is an n+-type source region, 15B is an n-type drain region 16A is a p-type source region, 16B is a p-type drain region 7A, 17B, 17C are resist pattern,
112 is a polycrystalline silicon film, 112B, 112c is a covering pattern, 114A, 11
4B, 114C are low concentration P input areas, 1158, 11
5B, 115C are high concentration As” implanted regions, 116A,
116B and 116C are high-concentration B impregnated regions, OX is the first SiOx film, chz is the channel region. 71 ~ Nel Element Type Ga 屹鋒Mupe P Soy Makihata Book Child Type Heri it-ichilayer -12-i Mouth Diagram 2

Claims (2)

[Claims] (1) A first gate electrode disposed on the p-type region with a gate insulating film interposed therebetween, and conductive sidewalls formed in direct contact with both side surfaces of the first gate electrode, and the p-type region. a first n, each having a low impurity concentration, individually disposed in a lower region of each sidewall in the mold region;
a high impurity type source region and a first n-type drain region; an n-channel MIS transistor having a second n-type source region and a second n-type drain region having a high concentration; a second gate electrode disposed on the n-type region with a gate insulating film interposed therebetween; a p-channel MIS transistor having a p-type source region and a p-type drain region having a high impurity concentration, the n-type region having an inner end surface in contact with the lower region of the second gate electrode; A CMOS semiconductor device characterized by: (2) It has a p-type region and an n-type region that serve as an element formation substrate, and defines and exposes the element formation region and contact formation region of the p-type substrate, and the element formation region and contact formation region of the n-type substrate. forming a gate insulating film on the semiconductor substrate exposed in each of the openings of the semiconductor processing substrate on which the field insulating film having the first, second, third, and fourth openings is formed; , forming a first conductive film having a first insulating film on the upper surface on the substrate to be processed; patterning the first conductive film in alignment with a first mask; a first gate electrode extending over the first opening of the film and having a first insulating film on an upper surface;
forming first and second covering patterns covering the openings of the field insulation film and the second openings and having a first insulating film on the upper surface; introducing a first n-type impurity using the gate electrode as a mask to form n-type low impurity concentration source and drain regions whose inner end surfaces are self-aligned with each side surface of the first gate electrode; forming a second conductive film on the substrate and etching back the second conductive film to form second conductive film sidewalls on both sides of the first gate electrode; , introducing a second n-type impurity through the first opening of the field insulating film using the first gate electrode having the sidewall as a mask, so that the inner end face is self-aligned with the outer end face of each sidewall. forming n-type high impurity concentration source and drain regions, and introducing the second n-type impurity through the fourth opening to form an n-type high impurity concentration base contact region; A second coating pattern is formed on the first coating pattern in alignment with the mask.
forming a first resist pattern corresponding to the gate electrode of the field insulating film, and forming second and third resist patterns covering the first and fourth openings of the field insulating film; selectively etching away the first covering pattern using the resist pattern as a mask to form a second gate electrode on the third opening of the field insulating film, and etching away the second covering pattern; Introducing p-type impurities through a third opening in the field insulating film using the second gate electrode as a mask to form a p-type impurity whose inner end surface is self-aligned with each side surface of the second gate electrode. While forming source and drain regions with high impurity concentration,
A method of manufacturing a CMOS semiconductor device, comprising the step of introducing the p-type impurity through the second opening to form a p-type high impurity concentration base contact region.