JPH0332030A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to manufacture an insulated gate type transistor in an LDD structure having excellent controllability by depositing an Si thin film on the entire surface, thereafter forming Si spacers on the side surfaces of a gate electrode. CONSTITUTION:A field oxide film 9 is provided on a p-type Si substrate 1. After a gate oxide film 2 is formed, a gate electrode film 3 of polycrystalline Si and a cap insulating film 4 are deposited. The gate electrode 3 is formed by selective etching. With the gate electrode 3 as a mask, n-type ions are implanted, and n-type source and drain regions 11 and 12 are formed. Then, polycrystalline Si is deposited on the entire surface as an Si thin film 5. Si spacers 51 and 52 are provided by anisotropic etching. Thereafter, with the spacers 51 and 52 as masks, n<+> source and drain regions 21 and 22 are formed. An interlayer insulating film 8 is deposited. Contact holes are formed, and metal wirings 31 and 32 are provided. In this constitution, the control of the width of the spacer becomes easy. The insulated-gate type transistor having a Lightly Doped Drain(LDD) structure having excellent controllability can be manufactured.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to LDD (Lightly Doped
The present invention relates to an insulated gate type MOS transistor having a drain structure and a method for manufacturing an integrated circuit thereof.

[Summary of the invention]

After depositing the gate insulating film on the semiconductor region of one conductivity type, the gate electrode film and the cap on it are removed. Two layers of film are deposited and selectively etched to form the gate electrode. Ions of the opposite conductivity type are poured into the one conductivity type region to provide a low impurity density source/drain region, and a Si thin film is deposited on the entire surface, and anisotropic etching is performed to form a Si thin film along the side surfaces of the gate electrode.
Provide an i-spacer. This method of manufacturing an LDD-MOS includes the step of again performing ion implantation of the opposite conductivity type to provide high impurity density source/drain regions. The spacer width can be adjusted by oxidizing the Si spacer, and polyimide can also be used as the gate electrode film.

[Conventional technology]

The LDD structure is effective in preventing reliability deterioration due to hot electrons, which becomes a problem when transistors are miniaturized. The general manufacturing method for LDD-MOS is to form the gate electrode with polycrystalline Si and then to form the source/drain 9N with low impurity density.
A region is formed by ion implantation, a spacer is usually formed on the side surface of the gate Ti electrode by Sing, and a source/drain region with a high impurity density is formed by ion implantation again. Polycrystalline S
Below i is usually a gate oxide film or a field oxide film, which is a film of the same quality as the spacer. Spacer formation is done by CVD oxide film
After deposition, the entire surface is etched by anisotropic etching. Therefore, it is difficult to detect the end point of etching.
As a result, there is a problem that the gate oxide film and the field oxide film also become thin. Furthermore, it is difficult to control the width of the spacer, resulting in poor reproducibility of transistor characteristics and integrated circuit characteristics.If the gate electrode is made of polycide consisting of silicide and polycrystalline Si, the oxidation process and 5ift spacer formation process described above There is also the problem that the silicide easily peels off due to the stress induced in the LDD-MOS, making it difficult to manufacture LDD-MOS.

[Problem to be solved by the invention]

The present invention has been made to solve the problems mentioned above.', 1177
The present invention provides a method for manufacturing an LDD-MOS with good monolithicity.

C! ! Means for Solving IB] The method for manufacturing an LDD-MOS according to the present invention is to deposit a gate oxide film on a conductive type semiconductor region, then deposit a 2N film as a cap insulating film on the gate electrode i1M, and selectively etching the gate electrode i1M. After forming an electrode and implanting opposite conductivity type ions into the one conductivity type region using the electrode as a mask to provide a low impurity density source/drain region (LDD), and depositing a 5iil film on the entire surface, a step of providing Si spacers along the side surfaces of the gate electrode by Si anisotropic etching;
This step is omitted from the step of implanting opposite conductivity type ions into the one conductivity type region using the i spacer as a mask to form high impurity density source/drain regions. Furthermore, the spacer width can be adjusted to tM by oxidizing the Si spacer, and polycide can also be easily used as the gate electrode film.

[Effect]

Si anisotropic etching can easily achieve a selectivity of 10 or more with respect to the oxide film, and can also detect the end point, making it easy to control the spacer width.Furthermore, since the spacer is made of the same material as the substrate, stress can be reduced. Furthermore, by oxidizing this Si spacer, the width of the spacer can be controlled within a range from about the Si film thickness to twice the Si film thickness.

On the other hand, when the gate electrode is made of polycide, the polycide is covered with a cap insulating film on the side surfaces by Si spacers, which makes it difficult to peel off due to the influence of oxidation.

(Example〕 The present invention will be explained in detail below using the drawings.

[11 Example 1 (Figure 1) Figure 1 (Al is, for example, after forming a field oxide film 9 on a p-type Si substrate 1 by the usual selective oxidation method, and further forming a gate oxide film 2, polycrystalline Si is formed. This is a cross section of the gate electrode 3 created by selective etching, which is similar to the manufacturing of a normal MOS transistor. N source/drain regions 11 and 12 are provided. However, in the present invention, a cap insulating film 4 is further deposited on the gate electrode film 3 made of polycrystalline Si, and selectively etched at the same time. A several thousand oxide film is used for the cap insulating film 4, and is selectively etched by reactive ion etching (RIB) at the same time as the gate electrode film 3 or in a different device. Although the resistivity of the ASI thin film 5 in which polycrystalline Si is deposited over the entire surface as 5ifilPJ 5 in FIG.
Polycrystalline material is used, the thickness is thicker than half the width of the spacer when forming the LDD, and the thickness is typically 1,000 to 4,000, and is selected depending on the purpose. FIG. 1 fcl shows a state in which Si spacers 51 and 52 are provided by anisotropically etching the Si thin film 5.
RI using gases of the F, CI, (,,1 is an integer) system
E is available. Since the selectivity to the oxide film is greater than IO, there is an advantage that the gate oxide film 2 and the oxide film 9 are less reduced during the formation of the spacers 51 and 52, and the end point can be easily detected. After this, the width of the spacer can be adjusted by oxidizing the Si spacers 51 and 52 as described in Example 2.
In this embodiment, a case without this v74 alignment process will be explained.

Figure 1 +d+ is n using Si spacers 51 and 52 as a mask.
This is a cross section in which source/drain regions 21 and 22 are formed. Fig. 1 ta+ shows a completed cross section, and after Fig. 1 fdl, a glabellar insulating film 8 is deposited, contact holes are opened, and metal wiring 31° 32 is formed.Although not shown in Fig. 0, the gate is Contact to the pole 3 is also made by opening a hole in the cap insulating film 4. The presence of the Si spacers 51 and 52 increases parasitic capacitance, but if this becomes a problem, please refer to Figure 1 fc.
) or Figure 1! After the step d+, the Si spacer 51.
This can be solved by oxidizing 52.

(2) Example 2 (Fig. 2) Fig. 2 shows an example in which the present invention is applied to a polycide gate, and a spacer width obtained by oxidizing a Si spacer. Although both are independent examples, they will be explained at the same time. Figure 2 (al is a cross section formed in the same process as Figure 1 (C1). However, the gate electrode film is polycrystalline S
It has a two-layer structure of iH3 and silicide film 6. For silicide rfJ6, for example, 1
MOS1x etc. are used for 1Si. Figure 2 (b
l oxidizes a part of the Si spacers 51 and 52 to form Si
An n@in@ spacer width 34 is provided to form an n'7-s drain region 21.22. Si spacer 51
．． By oxidizing 52, the spacer width can be increased by about half the oxide film thickness. This shows that the Si spacer width can be controlled to a predetermined width in the oxidation process as long as it is approximately half or more of the predetermined space width.
In the spacer, the spacer width is almost uniquely determined by the thickness of the gate 1!1 pole and the thickness of the Si0g film for the spacer, but according to the present invention, the spacer width can be freely controlled by oxidation of the aSi spacer and n9 If the ion implantation for source/drain formation is performed in stages, it is possible to integrate various types of MOSs with different LDD widths. Even when the gate electrode is made of polycide, the presence of the cap insulating film 4 can prevent the Si spacers 51 and 52 from peeling off due to oxidation.

〔Effect of the invention〕

As described above, according to the present invention, conventional etching techniques can easily (11) controllability and reproducibility, +21 L DD
LDD-MOS, whose width can be easily adjusted, can be manufactured into LDD-type insulated gate transistors for boat fishing. Furthermore, the present invention can be applied to a two-layer structure of polycrystal and silicide, so-called polycide, and has the advantage that conventional problems with polycide can be overcome.

Although polycide has been mainly described as an example, the present invention is also applicable to a gate electrode structure made only of high-melting point metals such as W and silicide, and to a two-layer structure with polycrystalline Si. Mainly NMO
Although the embodiment was explained in Section 3, it can of course be applied to both PMO5 and 0MO3.The present invention is applicable not only to the production of fine MOS transistors with a gate length of 1.5μ or less and their integrated circuits, but also to the production of high voltage MOS. It is also particularly effective.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view along the manufacturing process of an LDD-MOS according to the present invention, and FIG. 2 is a cross-sectional view of the manufacturing process according to another embodiment of the present invention. ■...p-5i substrate 2...Gate oxide film 3...Polycrystalline gate electrode 5...Si thin film 6... -Silicide film 9...Field oxide film 11, 12...n- Source/drain regions 21, 22
...n1 source/drain regions 51, 52...Si
Spacers 53, 54... oxide film or more

Claims (3)

[Claims] (1) In a method for manufacturing an insulated gate transistor having an LDD structure, a first step of depositing a gate insulating film on a semiconductor region of one conductivity type in which the transistor is to be formed, and then depositing a gate electrode film and a cap insulating film; , selectively etching the cap insulating film and the gate electrode film to form a gate electrode, and using the electrode as a mask, ions of opposite conductivity type are implanted into the one conductivity type region to form low impurity density source/drain regions. a second step of depositing a Si thin film over the entire surface, and then subjecting the thin film to anisotropic etching to form a Si spacer along a side surface of the gate electrode; a third step of masking the gate electrode and the Si spacer; and a fourth step of implanting opposite conductivity type ions into the one conductivity type region to provide high impurity density source/drain regions. (2) After the third step, at least a portion of the Si spacer is oxidized to form a part of the spacer, and after controlling the width of the spacer, the fourth step is performed. A method of manufacturing the semiconductor device described above. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode film is composed of a polycrystalline Si film and a high melting point metal film or a high melting point metal silicide film thereon.