JPH01149573A - Image sensor reading circuit - Google Patents

Abstract

PURPOSE:To reduce the jitter of an amplifier output, to improve a reading speed and, simultaneously, to stabilize an action by providing a reading timing correcting signal generating means and correcting a timing to read the output of an image sensor. CONSTITUTION:In the generation of a reading timing correcting signal, first, a differentiation zero is set by using a differentiator 17 and a zero-cross detector 18 for detecting maximum value. Next, time from the rise of a reference clock signal up to a point where an amplifier 15 output is maximum is measured and stored into a RAM 20, simultaneously, the time from the rise of the reference clock up to the differentiation zero is measured by a timing counter 19, and it is stored into the RAM 20. At the time of reading, data stored in the RAM 20 are used, and the clock, in which the jitter is corrected, is generated by a clock generator 11. Thus, in the view of the reference clock, the amplifier output, in which the jitter does not exist, can be obtained. Namely, the jitter of the amplifier output can be reduced, the reading speed can be improved, and simultaneously, the gradation of a density can be stably held.

Description

[Detailed description of the invention] extreme selection The present invention relates to an image sensor reading circuit.

Prior art Fig. 3 is a block diagram for explaining an example of a general image sensor unit using peak hold. In the figure, 1 is a timing signal generation circuit, 2 is a shift register, and 3 is a sensor driving transistor. , 4 is a sensor element, 5
is an amplifier, 6 is a peak hold circuit, and 7 is an image processing (A
/D conversion) circuit.

As is well known, in order to obtain a signal output from linearly arranged sensor elements 4 according to the amount of light incident on the sensor elements, the drive transistors 3 corresponding to the sensor elements 4 are turned on one after another by the shift register 2. After passing the output signal of the sensor element 4 through the amplifier 5, its maximum value is fixed by the peak hold circuit 6, and the output signal from the sensor element 4 is fixed by the peak hold circuit 6.
handed over to.

Thereafter, the peak hold circuit 6 is reset by a reset signal from the timing generation circuit 1, and the above-described operation is repeated to read the line sensor.

FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. 3, and shows only one element of the sensor. (b) The figure shows the output of the shift register 2 (sensor drive transistor ON signal), (c) the figure shows the amplifier 5
(d) is the output signal of the peak hold circuit 6, (e) is the reset signal generated by the timing generation circuit 1, B in (c) is the jitter, and C in (d) is the output signal. It shows A/D conversion time.

Now, if you try to read an A4 size manuscript at 2.5 m5ec per line, the clock cycle will be about 1 μsec. As mentioned above, FIG. 4 shows a simplified representation of only one element of the sensor, but the clock ((
a) Variations in the rise time in figure), variations in the shift register, and rise in the drive transistor ((b)
The maximum point of the amplifier output (Figure (C)) becomes earlier or later in the time axis direction due to variations in (Figure).
(C) Easier to understand than Figure B). Furthermore, if the sensor is divided into several blocks and multiple amplifiers 5 are used, variations in delay between the amplifiers must also be taken into account. During the A/D conversion time (C in the diagram (d)), the maximum value of the amplifier output must be held by the peak hold circuit. However, the maximum value of the amplifier output fluctuates in the time axis direction due to the above-mentioned reason (see jitter in Figure B ((C)), so it takes a long time for peak hold to stabilize.

Further, for the same reason, the same thing occurs in subsequent clocks, so that the A/D conversion time (see Figure C in (d)), which is the flat part of the peak hold, becomes shorter.

This requires a high speed A/D converter and increases cost. Furthermore, it is obvious that problems will occur if reading is performed at even higher speeds.

As mentioned above, when considering the rise time of the sensor driving transistor, the timing of the shift register, the delay between amplifiers, and their changes with respect to temperature and changes over time, the output from the sensor reading circuit will fluctuate in the time axis direction ( jitter). For this reason, when attempting to increase the reading speed of the document, the jitter causes the output to have a longer undefined portion, which requires a large time margin, which is an obstacle to increasing the speed.

Purpose The present invention was made in view of the above-mentioned circumstances.
Particularly, in an image sensor reading circuit, the purpose of this invention is to reduce the jitter of the amplifier output, improve the reading speed, and obtain stable operation.

Configuration In order to achieve the above object, the present invention includes a reading timing correction signal generating means in an image sensor reading circuit, and corrects the timing of reading the output of the image sensor by the reading timing correction signal generating circuit. It is characterized by this. below,
An explanation will be given based on an example of the present invention.

FIG. 1 is a block diagram for explaining one embodiment of an image sensor reading circuit according to the present invention, in which 10 is a reference clock circuit, 11 is a clock generator, 12 is a shift register, and 13 is a sensor driving transistor. , 14
1 is a sensor element, 15 is an amplifier, 16 is a peak hold circuit, 17 is a differentiation circuit, 18 is a zero cross detector, 1
9 is a timing counter, 20 is a RAM, 21 is a reset timing generator, 22 is an image processing circuit, and 1 image processing circuit 22 is provided to avoid unevenness on the original due to variations in sensor bits or light source.

Read the standard white original and store the amplitude data in RAM.
After that, the data is used to correct the gradation during reading. At that time, time data at the maximum point of the amplifier output is also collected by comparing the amplitude data with the reference clock. Note that the reference clock is composed of a stable oscillator such as a crystal oscillator.

FIG. 2 is a time chart for explaining the operation of the present invention, and (a) shows the output signal of the reference clock.

(b) The figure shows the output signal of the clock generator, Az.

A2. A and I are jitter correction values, and these correction values are
It is created based on the data input in 20.

First, the appropriate time from the rise of the clock to the point at which the amplifier output reaches its maximum is measured and stored in the RAM 20. For this purpose, a differentiator 17 and a zero cross detector 18 are used to detect the maximum value to obtain a differential zero. The time from the rise of the reference clock to zero differential is measured by a timing counter 19 and stored in the RAM 20. RA when reading
By using the data stored in M20, the clock generator 11 generates a clock (second
Figure (b)) is created, thereby making it possible to obtain an amplifier output with no jitter when viewed from the reference clock.

Effects As is clear from the above description, according to the present invention, the image sensor reading circuit is provided with a reading timing correction signal generation circuit that corrects the timing of reading the output of the image sensor, and the total value of the variation of each sensor element is calculated. By storing the data in memory in advance and using the stored data when reading, the jitter of the output of the image sensor amplifier is reduced, and
The reading speed of the image sensor can be improved and the density gradation can be kept stable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining one embodiment of an image sensor reading circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a conventional image sensor reading circuit. FIG. 4 is a block diagram for explaining an example of the image sensor reading circuit of FIG. 3, and FIG. 4 is a time chart for explaining the operation of the circuit of FIG. DESCRIPTION OF SYMBOLS 10... Reference clock circuit, 11... Clock generator, 12... Shift register, 13... Sensor drive transistor, 14... Sensor element, 15...
...Amplifier, 16...Peak hold circuit, 17...
・Differential circuit, 18...Zero cross detector, 19・
...Timing counter, 20...RAM, 21...
- Reset timing generator, 22... image processing circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] An image sensor reading circuit comprising a reading timing correction signal generating means, the reading timing correcting signal generating circuit correcting the timing of reading the output of the image sensor.